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AMD

AMD Shows Off 1.1 GHz Athlon 281

Posted by Hemos from the faster-and-faster-it-goes dept.
chamega writes "AMD demonstrated a 1.1 GHz processor Monday without any special cooling techniques. The processor is said to use "high-performance on-die Level 2 (L2) cache," whatever that means. " Perhaps, unlike Intel, they'll actually be able to /ship/ their high-end chips when they say they will.
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AMD Shows Off 1.1 GHz Athlon More

AMD Shows Off 1.1 GHz Athlon

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  • And here's what Dell thinks about it.. (Score:1)

    by Anonymous Coward
    This stor y [zdnet.com] tells what Dell think about AMD. One must wonder why on earth Michael Dell is considered a business genius!

  • Re:The cache on-chip finally? Yay! (Score:1)

    by Anonymous Coward
    Remember, the PPro was the first x86 to get on-chip, same speed as CPU, L2 cache. The P2 and P3 just built upon the PPro design.

    This is inexact.

    PPro had *integrated* L2 cache, but not on the same die as the processor itself. The PPro packaging contained the CPU core, and 1 or 2 dies of 256 (or 512 maybe) Kb of L2 cache, connected to the CPU core.

    To say it short, you had 3 silicon dies inside the PPro. Celeron-A, K6-3, Coppermine and future Athlon (Select, Thunderbird and Mustang) pack all the fun (functional units + cache) on the same silicon die.

    This makes the L2 on thoose processors more a huge-secondary-L1 than a real L2 cache, but I'm just nitpicking here ....

  • Re:Where is the G spot (Score:1)

    by Anonymous Coward
    All wrong. 1 GB (base 2 definition, in most peoples opinion the real definition of disk size) is 2^30 = 1.073.741.824 bytes. 1 GB (base 10 definition, used mainly by harddisk producers to make their disks look bigger) is 10^9 = 1.000.000.000 bytes. 10^9 * 1024 is 10^9 kB, about 1000 GB, and not following any intelligent definition at all.

  • but will this whip a Crusoe? or even a G3 (Score:2)

    by Anonymous Coward
    Mhz races are not a particularly good performance indicator, Apple are saying that the G3 does 1 Gigaflop, which might be a more interesting way of comparing chips, especially if the length of the flop is defined. to assess performance I think you need to consider: clock speed instruction set (RISC / CISC / MMX) word length any performance optimisation like code morphing.
  • AMD is working really hard trying to push a dual-proc chipset out, but are running behind schedule. Their first estimate was 'late 2000' and now it looks like 1H2001.

    I think they'll be called the Irongate 960 and 980 or something like that.

    Oh well. :(
  • If you remember correctly, it was JC News (dont remember the site, maybe jcnews.com?) that broke the story about the power cycling issue. JC himself had worked for Dell for a couple of months after being turned from temp to perm and they Dell fired him for it. JC claims that he got his info from someone else inside Dell, but they fired him because he was still in his probationary period, and they could.

    I agree for the most part with what Mike Dell said about AMD's incompatilility (tho its not true for current athlons), but don't paint him as an impartial observer.
  • You can find that review on Ars Technica [arstechnica.com].
    --
    Whether you think that you can, or that you can't, you are usually right.
  • Where's the mineral oil article, on supercooling got to... :) Ah! Here it is... You stick with 1.1 GHz, if you want. That's slow! :)

    I want to play XMame games under KDE under ARM Linux under the arcem ARM emulator under Gnome/Enlightenment under OpenBSD under the 80x86 emulator under Linux 2.2! And I want 'em playable!

    Seriously, this looks like one -very- nice processor. If they can get the scale down and have SMP on a single die, that would be even nicer!

  • Recently I read that even the fastest processors out (at the time of the writing) aren't quick enough for Quake III when you turn on all of the graphics features.

    I'm waiting for the processor which will do this smoothly; my P6-200 with Voodoo2 gets a little slow in 'Fast' mode when there are more than a few people on.

    --

  • The AMD-750 chipset doesn't do SMP, and neither does Via's new KX133 chipset -- the chip itself is ready for multiprocessor configurations, but nobody's made it feasible yet, and don't expect it for a while.

    I think it will be this year.

    Neither AMD nor VIA have announced a SMP chipset (AMD has stated the 750 is the only one they intend to do, they want other compines to to the "real" chipsets). I'm supprised VIA hasn't announced since they have done SMP PPro and other chipsets in the past.

    That doesn't mean nobody is making them. Both Hotrail [hotrail.com], and API (URL unknown) have announced SMP chipsets. They have given no firm dates that I know of. Hotrail initally said "in 2000", now they are saying in the second half, I think. They havn't blown a promised date yet, but they havn't made any strong promises.

    Again I know nothing about API, but Hotrail has made noide about 2-way, 4-way, 8-way, and "more". Also there is the dark horse of Compaq, after all they have SMP (and much bigger then 8-way!) systems using the same bus, but with a diffrent form factor, and possably diffrent speed and voltage.

    I don't know if it was a mistake for AMD not to do a sample multi-CPU chipset. Having a SMP chipset would let them sell more CPUs, and high-margin ones if they convince motherboard makers that it is too much trubble to get the non-Ultra Athalons to run more then two-way (they are claiming it is possable, but eletrical tolerences will be very tight, and for some reason it is easier with the Ultras).

  • I do know that there's a pretty fierce tradeoff between complexity and speed, though, and sometimes you get more milage out of keeping it simple but screaming fast.

    That was HP's feelings through most of the '90s. They used only a L1 cache, and it was off-chip. It was huge for the time, and very fast for an off-chip cache. I think the last design they did that way had 2ns SRAM (500Mhz if you ignore overhead). In the last year and a half they have moved to an on-chip cache, sometimes with an off chip L2 cache. They have fought the good fight against the Alpha for the number one SPECfloat spot for years, sometimes winning, sometimes coming in second.

    On the other hand the Alpha has almost allways had a small on-chip cache and a larger off chip one. Recent designs (21266) include a tiny "L0" cache (8K or 4K I think) and a larger L1 cache both on chip with a larger L2 off-chip cache. I expect your stament about having little predicability left by the time you get to a L3 cache really has less to do with the number of levels, but the size of each.

    I expect these tradeoffs change as the cost of on-die transistors changes, and even the speed of them. Back when 100Mhz (10ns cycle time) was fast, taking a 1ns trip across wires off the die was cheap. Now it is still the same cost to go off the die (say 1ns), but we want to run at 500Mhz or 1000Mhz (2ns to 1ns cycle times!), so that off the chip cost is now huge compaired to doing it on-chip.

  • To moderators: please moderate the above post up. This guy knows what he's talking about.

    And I just want to add one more thing. To all those whoe are saying bus speed is the bottleneck: did you actually run the benchmarks to compare the speeds? Where did you get this idea from? Perhaps you just assume higher bus speed will necessarily speed up the computer immensely.

    Well, there have been many benchmarks that show quite the opposite. The CPU is *not* limited by the bus speed. Even the 66MHz bus is more then enough to supply all the memory bandwidth the CPU needs. And that is why Celeron, with its 66MHz bus runs just as fast as "true Pentium 3" with its 100MHz bus.

    Statements like "processor speeds above 400MHz don't make that drastic difference" are made by really clueless people. Reality check: take a look at the actual benchmarks. Even when running 3d games like Q3, memory bandwidth is *not* a bottleneck. L2 cache compensates for slow RAM quite nicely.

    Of course, on the other hand, you don't need a 1.1GHz CPU to run a word processor/browse the interent. Well, not yet anyway (right, Bill? :-)

    ___
  • These days the video card is the bottleneck, not the CPU. Get GeForce (IMHO the only 3d card worth getting) and you'll see *huge* improvement in speed, even with the same CPU. Of course there is no P6 board that has AGP slot...

    But in any case, the video card is the limiting factor, not the CPU. And now that GeForce and a few other cards include the geometry engine which takes *all* graphics-related work away from the CPU and lets it do other things (like AI), even a P6-200 would work just as well. Then again, too bad no P6-200 board has AGP slot...


    ___
  • But RAM technology is becoming the bottleneck lately.

    Uhhh... I'm getting so tired of this. No RAM technology is NOT becomming a bottleneck. Tom (www.tomshardware.com [tomshardware.com]) tested p3-600MHz systems with standard pc100 SDRAM and 400MHz Rambus. Well, the Rambus systems were about 5% faster. But considering also that they had newer chipsets and, most importantly, on-die full-speed cache (as opposed to halh-speed cache of the old P3-600), one has to wonder what exactly caused the speed increase. Also, considering that Rambus is 6 *times* more expensive then SDRAM, the 5% speed increase does not look attractive at all.

    ___

  • Theoretically, what you are saying is true. However in practice it does not happen precisely because the curent memory bandwidth is enough. You also mention latency -- and yes, decreasing latency would benefit performance, but this is not what Rambus, PC133 SDRAM and DDR DRAM are designed to accomplish. Their goal is to increase the memory bandwidth which has nothing to do with latency.

    In the benchmark I mentioned, Tom used 400MHz Rambus -- the fastest one currently available. It has exactly twice the bandwidth of PC100 SDRAM (800MB/s vs 1.6GB/s). And yet the performance difference was a whopping 5% on *some* benchmarks, even less on most. Keep in mind that Rambus is no less then *six times* more expensive then standard SDRAM.

    Furthermore, there have been quite a number of benchmarks that show *no* difference in overall speed between 66MHz and 100MHz bus Pentium 2, given that the CPU speed is the same. Surprise surprise, cache is actually quite effective.

    Now, when you have a SMP system, you may eventually run into memory bandwidth problems as the clock speed and the number of the CPUs increase. But it is a non-issue when it comes to single-CPU machines, even when playing 3d Games (Q3 comes to mind).

    The real bottleneck is currently the video cards. NVidia GeForce and a few others include the geometry engine which takes care of *all* graphics related work. This is a step in the right direction. Even now the video card matter much more to a 3d game performance then the CPU and bus speed combined. And I expect the trend to continue.

    ___
  • I certainly agree with you here. It's nice to finally read a comment from somebody who actually understands what they are talking about.
    However, I don't see how PC133 SDRAM or DDR DRAM would decrease latency. Wouldn't it just increase the bandwidth the same way Rambus does? Care to explain, please?

    P.S. I should have said memory *bandwidth* is not the bottleneck. Lowering latency would certainly be helpful. Unfortunately Intel doesn't think so... or doesn't want to. Why does Intel insist on Rambus even now that it's clear the technology sucks?

    ___
  • but the bandwidth of PC100 SDRAM is 800MB/s.
    ___
  • Just curious, but are we talking Ghz as in 1024 Mhz or Ghz, as in 1000 Mhz.

    1 GHz = 1000 MHz. Hz are not specific to binary (i.e. computer) systems, so they use standard base 10.

  • Have you found an Athlon motherboard that runs the RAM at 133 MHz? I can't find one anywhere.

    Not yet - but I plan to slap a serious cooler on it and do some overclocking. I have the Asus K7M board, which has support for higher bus speeds. So PC133 doesn't cost much more (about $10 for a 128 MB stick), and has a higher margin of tolerance.

    I'm looking forward to the VIA chipset for Athlon (the Asus uses the AMD Northbridge, with a VIA Southbridge - the other current vendors use the full AMD chipset), as it should drive prices down and support PC133 RAM explicitly. But hey - I didn't want to wait. I can always build another Athlon system later on to run Linux on (my current one is my Win98 gaming PC and my Linux desktop is a PII-350).

    - -Josh Turiel

  • ...Darn! And I just bought a 600! (Score:5)

    by jht ( 5006 ) on Tuesday February 08, 2000 @04:46AM (#1296364) Homepage Journal
    Of course, I only paid $240 for my Athlon 600 processor, so I don't feel too deprived.

    To the people wondering just how a system with only a 200 MHz bus (and PC100 RAM, at that) can be useful at 1.1 GHz:

    First of all, if you're dropping the kind of change on one of these that is appropriate, you'll have more than a puny 64MB of RAM. It's liklier that you'll have at least 128 MB or probably 256 MB+. So you won't have a huge problem with disk thrashing. Just make sure if you were to use one of these beasts that the rest of the system is up to the task. That means a fast ATA or Ultra SCSI disk, a fast 3D card (don't be using no Rage Pro!), and the best memory that the system spec works with. I use all PC-133 nowadays.

    On the other side of this is the processor itself. On-die cache (Celerons, CuMine PIII processors) is much faster than the variety that is mounted on the PCB (older PII and III and current Athlons). It can run at full processor clock instead of, say, 1/2 clock or 2/5 clock. Because of this speed advantage, less of it goes a long way. Older PII and PIII designs used 512k of on-board cache, which is replaced by 256k of on-die in the CuMines (128k in the Celery). With a big, fast L2 cache a lot of your instructions are fetched from cache and executed much faster - and of course a big L1 cache helps, too. Also, SDRAM does a better job of feeding data in bursts than older EDO and FP RAM did. But RAM technology is becoming the bottleneck lately. Rambus and DDR SDRAM is supposed to help, but DDR isn't really there yet, and Rambus has been a fiasco to date and the yields are allegedly horrible.

    Ultimately, on-die cache allows the cache to run at either full CPU speed or a high divisor of it. PCB cache is more constrained. But faster processors will always make a difference no matter what - it's just that after you outrun the rest of the system it's a matter of diminishing returns. An Athlon 1000 is not necessarily exactly twice as fast as an Athlon 500 - but it's still wicked fast!

    - -Josh Turiel
  • Hmmm. Well I've built and used systems with: AMD 386DX/40, AMD 486DX4/100 K5 100, K5 133, K6 233, K6-2 300, and a K6-3 400, all in 7x24 server functions. I only had problems with the K6-2 300, which was really sensitive to the efficency of it's CPU fan, but still ran flawlessly for about a year before I retired it.

    All the rest (including the 386, minus the K6-2) are still in service somewhere in someone's computer and doing fine.

    When the K7 SMP systems arrive, that will be my next system. I've used almost nothing but AMD chips for the last 7 years (currently I'm running a dual 433 celeron system) and have nothing but good things to say about them. The only down side I can really find is that supporting chipsets (Via, SIS, etc) do not do some functions as well as the Intel equivilents, like PCI DMA throughput. Nothing wrong with the AMD chip, though..

    jf
  • The two of them have been playing "tit-for-tat" for some time now... I wonder how long Intel will be able to keep up that game. Not long, I'd wager. I wouldn't be suprised to find that they have no answer for this. Wilamette might be Intel's answer further down the road, but it is hard to say what with the K8 (and, yes, the K9) looking so nice. About production... That has been AMD's problem for a while. Anyone got any links indicating how well they have been able to meet the demand for K7's?
  • Despite spending $2*10^9, they are still behind AMD. Guess that demonstrates that you can't just throw money at something and expect to get the best results. More $ + more engineers != better chip. If that wasn't the case, you'd think Intel's huge budget would allow for good IA-32 _and_ IA-64 development.

    AMD certainly couldn't do IA-32 and IA-64 at the same time, true. And they aren't, so what does that matter? That is solely an issue of manpower. More manpower _does_ help when working on separate parallel projects, but not necessarily on one project -- again, that is why despite the $/numbers advantage, Intel is still behind.

    Have you forgotten that Itanium is just the marketing name of Merced, the chip that _Intel_ has already said will have sub-optimal performance and merely be a proof-of-concept IA-64 chip? That, and I am thoroughly unconvinced that IA-64 is the correct way to go. After studying (what has been published about) its microarchitecture, I see flaws that it is not clear they will be able to overcome. Most of the benefits of ia-64 are attainable in other ways.
  • The reason Intel will have a hard time keeping up with AMD is because Intel has pulled out all the stops on coppermine, and AMD has room for improvement. The i840 is indeed a very nice chipset, with RDRAM and AGP4x. Coppermine has on-chip cache at full core frequency. Desipte this, coppermine is only slightly ahead of Athlon.

    Remember when Intel went from off-chip to on-chip L2? They went from being creamed by Athlon to being comparable, on the slightly ahead side. What do you think will happen now that AMD has moved their L2 on-chip?

    The same can be said for chipsets. When better chipsets come out for K7 with DDR, K7 will benefit. Coppermine has already topped off. How much longer can a peaked-out system stay ahead?

    However, in chipsets we can agree I think that it is AMD's major weakness. In order to really let K7 show its true power, there has to be a chipset that has those features that would put it on par with the i840. AMD probably can't do this, due to manpower. VIA I believe can, but the question is will they? AMD's future is not at all clear.

    SMP athlons is of course a dream of every AMD-lover. It is very true that dual coppermines will beat a mono k7. Assuming, of course, you are running a multi-threaded app.

  • I don't believe it! A company announces and demo's a fairly major step forward in chip technology - running a really powerful processor as speeds of over 1 Mhz without any fancy cooling systems, and you want to know how fast it'll play a game?

    Hell Fucking YES!! Fuck specs and fuck MIPS. To hell with Mhz and GHz. Well does this bad boy Quake? In the long run that is all that matters.

  • Actually, I meant hard disks were a bottleneck in general, not necessarily in games. Sorry if it was a bit ambiguous.
  • You also mention latency -- and yes, decreasing latency would benefit performance, but this is not what Rambus, PC133 SDRAM and DDR DRAM are designed to accomplish

    Actually, you are correct that the goal of Rambus is not to decrease latency, but rather to increase bandwidth. You incorrect, however, when you state that PC133 and DDR SDRAM also have that goal. PC133 and DDR RAM have the goal of decreasing the latency, *not* increasing the bandwidth. Increasing the clock speed of the RAM (as PC133 does, and as DDR "fakes" by using both clock edges rather than just one) should cut the response time for the memory (latency). It doesn't affect the volume of data transferred on a clock cycle (bandwidth).

    Rambus increases bandwidth, yes, but at a cost to latency. This is why sometimes using Rambus memory will actually slow down the system - bandwidth (as you stated) is not the bottleneck. Latency, however, is more of a bottleneck. Accessing a piece of data from memory can take hundreds of CPU clock cycles, during which the CPU is often forced to stall and do nothing. Reducing this will certainly help performance, though how much depends on the specific application (and for many benchmarks, you will see little improvement - many of the benchmarks out there are intended to stress CPU performance, and as such are computation-heavy rather than I/O heavy. Applications that are more biased towards I/O operations will benefit more than others that are not). Heavy-duty multimedia can fall into the category of applications that will really benefit, since often the volume and rate of data being processed is so large that it means a smaller percentage of the data is accessed from the cache, and more from main memory.

    The real bottleneck is currently the video cards

    For games, I'd certainly agree. In general, hard disks are also an often-overlooked bottleneck.
  • However, I don't see how PC133 SDRAM or DDR DRAM would decrease latency. Wouldn't it just increase the bandwidth the same way Rambus does? Care to explain, please?

    As I understand it, the delays from when you send the memory an address to when you get the data that resides at that address consist of two major components: RAS/CAS delays (which is basically the memory figuring out which bits to return based on the address it's given) and then the delay from that point to when the output is ready. Each of these delays will take some number of clock cycles. So if you now increase the clock rate, from say 100 to 133MHz, the number of clock cycles remains the same but the overall time from when you supply the address to when you get data back is less. Which is a decrease in latency. (As opposed to bandwidth, which isn't a decrease in the time for a single piece of data to transfer, but rather how many pieces of data can be transferred at once).

    Now, I'm not very familiar with the way DDR works. It could very well be that a given piece of data still takes the same amount of time to access versus a equal-clock-rate Single Data Rate chip, but that the RAM can simply handle more transfers by using both clock edges. In that case DDR actually is targeting bandwidth, not latency. It might be that the DDR actually transfers a given piece of data twice as fast, but the more I think about it the less likely I see that as being. So you were probably correct about DDR targeting bandwidth not latency.

    As for bandwidth not being a bottleneck, it really does depend on the system. For your typical PC or low-end servers, more memory bandwidth doesn't really help much (if at all). For things like the next generation of video game consoles, it might help a lot. High-res video processing does require a *lot* of bandwidth, and something like Rambus might be very useful there (I think Nintendo or one of other the console makers is actually going to use Rambus in their next machine, I don't remember which one).

    For example, look at the GeForce video cards. Those that have DDR SDRAM instead of the standard SDRAM perform much better at high resolutions, because there's just a ton of data to transfer per clock. At low-res there's no real difference, presumably because the card isn't having to access too much data from the video memory. At high res, there is more data per frame, so each transfer has to accomodate more bits (needs higher bandwidth). Thus the DDR version keeps on churning out high frame rates when the SDR version starts having real trouble.

  • Agreed. I was just reading some stuff about the testing being done at those resolutions at IBM and realized that it was getting into the "within 5 years" realm. Can someone refresh my memory as to what the current lithography limit is? I mean, we're getting down into traces that are hundreds of atoms wide that we need to avoid voids in over wafer scale surfaces. I believe I also just read that Intel was just moving into .18 so AMD s leading the technology curve since they're already in copper production as well.

  • Smokin! (Score:3)

    by coreman ( 8656 ) on Tuesday February 08, 2000 @04:08AM (#1296374) Homepage
    And this is made on .18 fab lines which leaves .13 and .07 yet to come. This processor is going to have so much more in it that Intel isn't going to be able to play the matching gigahertz game much longer. You do have to admire a company that not so long ago had been totally written off and now has processors in most of the Intel strongholds. What's next? PPC overtaking Intel marketshare?
  • Oops! My bad. Sorry about that.
  • First of all, "k" should always be lowercase when used as a prefix. (Note that "k" should always be a PREFIX to a unit. "K" being used alone as you do above is merely colloquial and non-standard.)

    Secondly, he was talking about the distinction between computer prefixes and SI prefixes. (Ever notice how 1kb is 1024 bytes?) He was joking about the silliness of the computer industry (especially the hard-drive industry) in using two different definitions interchangeably, whichever suits them best.

    It makes you look really bad to put people down when you don't even seem to know what you're talking about yourself.
  • Actually, Michael Dell does have a point.

    Anandtech, Tom's Hardware and Sharky Extreme reported that the early Athlon motherboards had compatibility problems, notably with AGP implementation and some tests failing altogether. ZD Labs reported that their 3D Winbench 2000 and other benchmark tests failed on these motherboards.

    Fortunately, the arrival of the VIA Apollo KX133 chipset may alleviate this problem (motherboards based on the KX133 chipset should be available in the next 30 days).

  • Kryotech (Score:3)

    by Syberghost ( 10557 ) <syberghost@syber ... S.com minus poet> on Tuesday February 08, 2000 @05:33AM (#1296378)
    I cannot wait to see what Kryotech is going to do with this bad boy.

    If their past patterns hold true, we should see anything from 1.5Ghz to 2Ghz.

    Of course, lights will go off all down your street when you fire it up, and you'll be able to go get pizza and Jolt while you're waiting for it come up when you turn it on...
  • Unless you're program is so small that it runs entirely from the cache, today's smoking fast CPU will spend quite some time twidling their thumbs waiting for data...

    You assume that Rambus is far better than current SDRAM well, that's not sure at all, remenber that initially Rambus memory was supposed to work at far higher speed, and that many articles compared today RAM and Rambus and said that while the Rambus has a far higher maximum theoretical bandwith their latency wasn't very good, so in fact using Rambus may SLOW DOWN your system...
    Ironical don't you think ?

    Read Hennesy & Patterson "Computer architecture" to see why saying RAM is not a bottleneck is stupid, if we could afford it, there would be no DRAM, we would use only SRAM, unfortunately it costs much more... And even in this case a small memory is usually faster than a bigger memory so we would still have to use cache to profit of the locality of references...
  • Ok, Mr. Jesus killer, if you think you're so smart, what's better, an Audi A6 or a SAAB 9-5?
  • -I go to Rice, so figure out my email address

    Oh then I guess it must be jmott@fuckingstupidasss.edu!

  • Dell could have been right here. There were some problems with Irongate boards initially. For example most of the first FIC batches had to be recalled. I would also avoid calling VIA the best chipset in the world ;-)

    While Intel used to beat everyone because of their chipsets. Unfortunetly sinse the venerable BX they have not produced anything as stable as they used to...
  • >Recently I read that even the fastest processors out (at the time of the writing) aren't quick enough for Quake III
    >when you turn on all of the graphics features.

    I dunno...I play on a PIII-550/TNT2 Ultra box fairly
    regularly, and /I/ don't notice any slowdowns, even
    with high quality and 1024x768 res.

    Of course this is Demo only, and I'm not really a
    hardcore gamer either, so I might be missing something...

    =-=-=-=-=-=
    "...You and me baby ain't nothin' but mammals/
    so let's do it like they do on the Discovery channel..."
  • In this article [zdnet.com], Michael Dell (of Dell Computers if you didn't know) says "We found the AMD environment to be much more fragile ... than equivalent Intel systems."

    This could be a Dell playing friends with Intel so he doesn't get short changed in chips when processor shortages come around, but none the less, his opinion will matter with big business about Intel being better than AMD.

    He goes on in the article to say that the chipsets are what is lacking for AMD.

    MHz is starting to become insignifacant compared to the overall system since the bus, hard drive, network, and RAM can't keep up. Once these technologies are sped up by an order of magnitude, we will see real dividends by these MHz increases.

  • I just bought a 600
    [snip]
    I use all PC-133 nowadays.

    Have you found an Athlon motherboard that runs the RAM at 133 MHz? I can't find one anywhere.


    ---

  • What's next? PPC overtaking Intel marketshare?

    Unfortunately, part of the Athlon's success is due to the fact that there's still a lot of demand for legacy x86. AMD is laking the low road, and it's paying off. I don't think this bodes well for PPC (or Intel's upcoming 64-bit CPU).

    Motorola needs to get off their asses on PPC. They'll never get leading marketshare if they don't learn how to supply the existing PPC demand. I have wanted to buy a generic (non-Mac) PPC [openppc.org] box for a long time, but there have been so many delays with everything from CPUs to memory controller shortages, that even Apple is having to slow down and wait. It's getting to the point where I'm about to lose my patience, wimp out, and get an Athlon. (And that's a shame, because this is for a box that's going to be on 24/7, where PPC's lower power usage would be attractive.) Failing to sell PPCs to people who want them, isn't a good way to gain marketshare. Motorola must have ex-Commodore people working for them.


    ---

  • Or they simply don't care about server market?

    Oh come on, we all know what you really mean. Just say it: the Quake 3 market.


    ---
  • Heck, I've got Karma coming out the wazoo!

    $|4$|=||>0+ $|_|><
  • Didn't Intel make a move to kill off VIA recently?

    I don't remember the specifics, but the gist of it was a lawsuit Intel brought against VIA when they bought Cyrix for its x86 compatible chip designs. Ostensibly the lawsuit was over the old "microcode patent infringement" bruhaha, but a couple of articles in the press said the real motive was to scuttle the AMD chipsets that VIA is bringing to market.

    Anyone with better knowledge of this care to comment?
  • I dont think michigan is in the Eastern time zone. Not sure about it but I think they're in Central.
    ___________________
  • this map [navy.mil] shows the time zones, but i'm not sure where Michigan is on the map... I know, I should know my geography,

    <sarcasm>

    but... it's Michigan for god's sake.

    </sarcasm>
    ___________________
  • This is not just a demo of a new product! This is demonstration of leading edge technology(.18u with copper interconnects) for their market segment. This also shows that their huge loans for building Fab30 in dresden paid off.

    I might be wrong, but whether in volume or not wouldn't this be the first real product to come off the Dresden fab?

    It would seem they have learned a valuable lesson: don't flaunt chips that don't exist. I got burned real bad last year when everyone thought they were doing so well, and they were. It was just at the expense of revenue, which hurt a lot of stock holders(like myself). Before the K7(erm, 'scuse me. Athlon) was released, I as a personal investor tried to find about it as much as possible. Info was out there, but not too much was said until they taped out. Now they don't really warn us, they just spring new products on us and that is good!

  • Microwave ovens uses 2.405Ghz. Perhaps in 2-3 years.... would be fun though. Just imagine having to use radiation shielding in a PC...

    Actually, the Federal Communications Commission is starting to worry about this sort of thing. As I understand it, internal lock isn't quite so important, but now that the front-side bus is getting into the 200 - 400 MHz range, RF emissions from leakage could be a serious threat to certain existing radio systems. With so many PCs being built by random people who don't care about RF sheilding, they are not sure what to do, but limitations on what do-it-yourself'ers can do have been discussed.

  • Grumble accually I was more trying to make a point, and an inquiry. As there is a chance that AMD could have defined GHz to be 1024 MHz, incorrectly. But, just to let you know, I generally start out with a mod of 2, and I guess somebody thought it was an interesting point, and if nothing else, there was a conversation surrounding it, one of which some people might find "interesting," or even "insightful." Because frankly when using points to sort the comments I see, I'm not always as interested in the comment itself, but the conversation below that comment as well, which will only be generally seen promenently(spelling?) if the base thread comment has a high enough score.
  • Just curious, but are we talking Ghz as in 1024 Mhz or Ghz, as in 1000 Mhz.. :)
  • <em>What company do you know that doesn't advertise its products before they are released?</em>

    Transmeta's the closest. (..and even they put up info on their website before then)
  • Here's how to fix it - get an account, then you too could become a moderator!!!

    Moderators are just readers. They could be me, they could be you, they could be a six year old. If you don't like the current make-up of the moderation pool, then by joining you can change the makeup of the moderation pool and thus how posts are moderated.

    I also have to disagree with you on Usenet being a much better model than /. - I use /. more than Usenet now exactly because in general, the moderated comments are usually better than the lower ranked ones and thus I can get more interesting reading in a shorted time than I can in just about any Usenet group.

    /. moderation is by no means perfect, but I'll take it any day over the complete chaos that is a normal usenet group, or the total control imposed by moderated newsgroups. I think of the user contributed moderation as being one of /.'s best features, and it's why I keep coming back.
  • That's standard legal mumbo jumbo, and not applicable at that. The chips aren't produced in the USA, but in Dresden, Germany, using wafersteppers from ASML, from Holland.

    Produced in the EC, America has lost yet another lead in electronics.



    ----------------------------------------------
  • Well, the only real limit would be whatever the size of three silicon atoms is. I believe that is all you need to create a transistor (someone correct me if I'm wrong).

    Well, you're wrong. The mechanics of silicium transistors is based on differences in material. To archieve these differences, silicium is poisoned with electron donors or acceptors. Hence P-material (named after phosfor, an electron donating element often used) an N-material (named after nitrogen, an electron accepting material). It's switching effect comes from the interaction between these materials, and can never be archieved with single atoms.


    ----------------------------------------------
  • Hehehe... :)

    Which reminds me. Today, VexMon had it's first proper stress-testing... VexMon on top of VexMon. Almost full speed. It started to grind about 7 or 8 levels deep, by which time I'd long since got bored, split some of them, and was running various Win95's, a SuSE Linux, a DOS 3.3 and an Atari STe running Cybercon III (which, chillingly, ran at about the right speed). :)

    ... and then, about six layers came crashing down, but at least I was still able to use the VexMon layer above to find out *why*.

    (Of course, the trick in running layers deeply, is remembering how to get out again. I had to interrupt then switch off!)

    I love this project. It's fun. :)
  • How do you use all this power with bus speeds only up to 200MHz (or even less in Intel's case)? I am pretty sure that processor speeds above 400MHz don't make that drastic difference.. in most 'processing intensive' applications, like gaming and image processing, performance increase is reached with more ram or a graphic card with, again, more memory.

    besides, with little memory, when system starts to swap, all the MHz don't matter all of the sudden because hard drive is *slow*. So, all the speed is reduced to the hd's speed.

    with these two constraints, bus speed and hard drive's speed, processor speed doesn't play that big role anymore, unless there are newer (faster) system bus / hd technologies or different architechture comes about.

  • And where can I get a Dual 733 i840 board, and the processors? Oh wait, you mean I have to wait a month or two? No thanks.

    THAT is the reality with going with Intel right now. They aren't just behind, they're so far behind they can't see the dust that AMD is leaving them in.

    In all seriousness, the i840 is hard to come by, and any cuMine processor over 650 is hard to come by. Intel announced an 800Mhz part, but I have yet to so much as hear a PEEP from my suppliers about it. Ditto the 750. I can run down and get a 750Mhz Athlon right NOW. AMD is kicking Intels ass on the supply front. THAT is what matters. SMP and such is on it's way, hell, it's not like AMD is making the chipset for it. If they were, we'd likely have it, but we'd have to go through a Fester-like period while VIA, or ALI got there acts together on cloning it.

    SMP will be out this year. It will rock. Hell, every benchmark I saw with a 733cuMine in the i820 has an Athlon 700 -STILL- beating it. The scores were close, but AMD still won. EVEN WITH the cache speed hit.

    C'mon, keep it up :)
  • AMD DEMONSTRATES 1.1GHz AMD ATHLONâ PROCESSOR
    - AMD Athlonâ Processor Built on Advanced Copper Technology Shatters GigaHertz (1000MHz) Barrier-

    SUNNYVALE, CA--February 7, 2000--AMD today demonstrated a 1.1 GHz(1100 MHz) version of the AMD Athlonâ processor...

    From the AMD Press Release [amd.com] (Emphasis mine)
  • Most of those compatability problems were cleared up with BIOS changes and the few that weren't were cleared up with the second generation chipset from AMD which has been avaiable for some time. The Via chipset will hopefully take the burden off of AMD (who incidentally doesn't want to be in the chipset business) but don't believe the Dell crap. Dell is little more than an Intel distributor so I wouldn't believe a word tehy say about AMD. 9 ot the top 10 PC manufacturers have all put forth AMD based sytems. Somehow, I doubt that they are all wrong and Dell is right.

    Asa
    (posted with a Mozilla M14 build from 2/7/00)

  • Put that in your Furby and smoke it!
  • On the Coppermine (PIII 'E'), when the processor asks for a specific portion of memory, if it's in L1 then it takes 3 cycles to be retrieved. If it's in L2 instead, then it takes 7 cycles (or so?) to be retrieved.

    That's basically the difference. They both 'tick' at the same clock rate, but one just happens to be able to deliver data in less than half the time.

    This is why I'm always pissed at people who ignore every other factor when they refer to "full speed" cache. I mean ... if you had L2 cache running at 800MHz on an 800MHz processor, but that L2 cache was only 8 bits wide and took eighty cycles to retrieve a piece of memory (eg, making it probably even slower than SDRAM), should you really refer to it as "full speed"?

    -JC
    PC News'n'Links
    http://www.jc-news.com/pc [jc-news.com]

    PS: Apologies ... in an earlier post, I referred to Willamette's bus as being 128-bit. I was very incorrect. The correct width is 64-bit (incidentally making Willamette's bus less cool than I thought).
  • ah yes, but what about 1600x1200? That's *real* gaming for ya 8^)
  • As has been posted on every Athlon thread since the beginning of time, the chip is ready for SMP, but the chipset isn't. The chipset for Athlon SMP is far more complicated (and higher performance) than that for the intel SMP structure. Check out the Alpha bus documentation for a little more flavor on this - its the same bus the Athlon uses, and the idea is to implement a crossbar switch rather than a shared bus. Cool, but costly.
  • For the same reason it's not likely (but you never know) that there's any advantage to adding an off-chip L3 cache.

    A price/performance advantage or a performance advantage? I would imagine that for a chip running at 1.1 GHz that access to a L3 cache running at 500 MHz would be far more perferable to access of some PC-266 Double Rate DRAM. The inhibiting factor becomes how much that 500 MHz DDR-DRAM is going to set you back, plus the complexity costs in you northbridge design, and that zingers that throws into cache coherenecy in multiple CPU designs.

    Even the performance advantage disappears if the hit rate isn't pretty high, because you insert at least one cycle into your access latency while you check tags for a hit. I'm not familiar with the studies themselves but from second-hand sources it looks like there's precious little predictability left in the access stream once L1+L2 get done with it.

    dpilot argued that the L3 cache on K6-3 systems adds measurably to performance; I certainly can't prove dpilot wrong. I do know that there's a pretty fierce tradeoff between complexity and speed, though, and sometimes you get more milage out of keeping it simple but screaming fast.

  • "On-Chip L2 cache" whatever that is (Score:4)

    by overshoot ( 39700 ) on Tuesday February 08, 2000 @07:43AM (#1296410)
    L1 cache is the memory closest to the actual computing functions. It runs at CPU speed, but because larger => slower it can't be very big; usually measured in Kbytes. It caches the most-used memory addresses.

    L2 cache is larger and slower than L1. Until recently, L2 was implemented by separate RAM devices attached to the CPU. The original Pentium (socket 7) L2 cache was on the processor's front-side bus, between it and the system controller. This became a serious speed limiter and newer processors added a back-side bus strictly for cache (one reason that the CPU modules appeared.) Back-side bus cache runs around 400 MHz plus three or so bus cycles added latency. At 800 MHz this starts to get ugly.

    Moving the L2 cache on-chip may not let it run much faster (typically CPU/2 or CPU/2.5) but it cuts the pipeline latency, and latency reduction is what cache is all about. Also, being on-chip makes it much less expensive to use wide busses so the L2 could, for instance, transfer an entire cache line to the L1 in a single cycle.

    L1+L2 cache is so good at removing nonrandom accesses from the memory stream that appears on the front-side bus that what actually makes it to the DRAM is almost completely random-access. That's why packet-based memory (e.g., RAMBUS) do so poorly compared to their sustained bandwidth: the bandwidth is never sustained, it's just the first cycle that counts.

    For the same reason it's not likely (but you never know) that there's any advantage to adding an off-chip L3 cache. The hit rate would be too low to be worth the trouble of checking for a hit.
  • Oh, please...
    Frequency is an analogue value. Not descrete. 1024 has no special meaning there.
  • ... is a *dual* Athlon system instead of MHz's.
    Is it just me or they are delaying SMP Athlon solutions for a bit too long? Or they simply don't care about server market?
  • Why don't you make an account, stop posting anonymously, earn a little "karma" and moderate for yourself?
  • Will it whip a Crusoe? The Crusoe is not really designed to run a billion MPH...it's mostly about low power consumption while still being able to do your work.

    Of course it will.
  • Time to go back to school puppy.

    CPU vendors do not test. CPU vendors sell.

    IC manufacturers test.

    You friend was joking. The only binning Motorola
    does regulary is for ancient commodity devices and
    I dont think there is much of that around anymore.
    Binning is a violation of SPC. Motorolas SPC
    program called Six Sigma is very stringent. It
    leaves little wiggle room for binning. Intel is
    ridiculed by the rest of the industry because of
    its continued use of multiple bins, 3, 4 or more
    bins!

    There are some instances when 2 bins can be used
    and still have a process that is in control. In
    any case in the 10 years I worked for Motorola,
    in IC Test engineering, did I ever see any
    binning.

  • SCSI Ultra3 (U160) is faster than Fibre Channel.
    SCSI Ultra4 will be faster than 2Gig Fibre Channel, and will show up before it.
  • Super Socket 7!
    Ya, getting to be real old tech, but they have AGP, even 2x! And Dimm support, and USB, and IR...
    When building cheap systems for folks, I usually take the SS7 and AMD|P6 route- good quality, stable (some annoying patches to deal with), zippy and cheap!
  • 1.21 Gigawatts!! Of course =)
  • Our ES box is positively aenemic in the clock speed department compared to our desktop intel boxen. And yes, when I do CPU intensive tasks, the desktop intel boxes will cream our rather old 167 MHz Ultra. However:
    - Our Sun boxes are reliable.
    - I think there's still a (narrowing) advantage on the IO/throughput side of things.
    - Other stuff
    Case point: A map I just did displays allmost instantly off our cruddy old ES box onto my even older Sparc5 desktop. Same map takes several minutes on a PII 300.
    Yes, I think Sun and SGI's lofty ground is being eroded, but there's more to big computing than clock speed.
    Xix.
  • I'm by no means an expert, but I believe the differentiation between on die L1 and L2 cache comes from different latency values. I don't know what the exact values are. But L1 is as fast a memory access as that processor is going to see. When L2 is on die, the processor will still be able to access it very quickly, but it might only be one half or one fourth as fast as the L1 cache (pulling numbers out of my ass).

    You weren't too far off. I just upgraded to a 450-MHz K6-III over the weekend and got these results from CacheChk (installed on an FIC VA-503+ v1.2 with the latest BIOS and 64 megs of PC66 SDRAM pushed to 100 MHz):

    CACHECHK V7 11/23/98 Copyright (c) 1995-98 by Ray Van Tassle. (-h for help)
    CMOS reports: conv_mem= 640K, ext_mem= 64,448K, Total RAM= 65,088K
    BIOS reports: ext_mem= 64,448K Total mem: 63 MB
    "AuthenticAMD" AMD-K6(tm) 3D+ Processor Clocked at 451.1 MHz
    Reading from memory.
    (timings snipped for some brevity :-) )
    This machine seems to have 3 caches! [reading] (This can't be right.)
    L1 cache is 32KB--1876.5 MB/s 0.6 ns/byte (1179%)
    L2 cache is 256KB--1257.8 MB/s 0.8 ns/byte (790%)
    L3 cache is 1024KB-- 480.1 MB/s 2.2 ns/byte (301%)
    Main memory speed -- 159.1 MB/s 6.6 ns/byte (100%) [reading] 11.3 clks
    Effective RAM access time (read ) is 52ns (a RAM bank is 8 bytes wide).
    Effective RAM access time (write) is 91ns (a RAM bank is 8 bytes wide).
    "AuthenticAMD" AMD-K6(tm) 3D+ Processor Clocked at 451.1 MHz. Cache ENABLED.
    Options: -t0 -z

    With the K6-III at least, L2 cache runs at about two-thirds of the speed of L1 cache. L3 cache, at 100 MHz, takes a big hit--it's only a little more than a fourth of the speed of L1 cache. L3 cache is still three times faster than main memory, though.

    (What's really funny is the comment about how it can't be right that there are three caches in this computer.)

  • K = 2^10, M = 2^20, G = 2^30 etc..
    k = 10^3, m = 10^6, g = 10^g etc..

    As many people have pointed out, powers of two have no special meaning when refering to frequency, which is analogue, so there's no point in using big G. So the number will be 1.1 gHz (= 1.02 GHz). Also it's in AMD's interest to quote gHz because the number is higher!

  • Giga == 10^9. Eg. 10^9 x 1024 bytes/k = 1 Gigabyte.

    Don't confuse Hz (cycles per second) with Bytes. So, indeed, 1000MHz == 1Ghz.

  • And true to form, you engineers 'borrowed' someone elses design. Which is why you can't sell it outside of mother Russia.
  • Good idea, but those letters are already taken. SI is case sensitive.

    M = 10^6
    m = 10^-3 (Remember mm's?)
    k = 10^3
    K = Kelvin (!)

    I found this link through Google [google.com]: http://www.ex.ac.uk/cimt/di ctunit/dictunit.htm#prefixes [ex.ac.uk] (Warning, the page is much larger than it has any business being.)
  • Hell, you ought to get a faster timedemo than that...

    Specs:

    k7/500
    fic sd11
    128mb cas2 sdram
    xentor tnt2/ultra (standard clock)
    sblive
    7200rpm ibm 34gxp

    EVERYTHING on at the highest settings:
    1024x768 16bit: 52.8fps (demo001)

    Something is off with your system...I still havn't gotten around to tweaking anything either (because I don't need to! :)
  • Then you don't know how to set one up right. Somehow I doubt you were using a good power supply -- those 200watters don't cut it when your cpu draws in excess of 50watts.

    Mine has been running perfectly since I've gotten it.
  • Nope, I don't have a SBP board; rev 1.8 of the board, stepping 4 of the chipset. My score is also with everything turned on...

    What brand of tnt2/ultra do you have? If it's the diammond one, that'd explain the difference. On every bench I've seen with a Diammond board, it's scored on average 10fps lower than it's nearest compeditor. The CLabs board is a bit better, but it's second from the bottom (where tnt2/ultras are concerned) if I remember right.

    I'm guessing the sblive is also helping make a bit of a difference. Probably worth a frame or two at most.

    If you have a bunch of software loaded to run in the background, that might be reducing your score some as well.
  • I do video-processing.
    Meaning, that I run 8*3*640*480*30 bits through the bus every second. Thats 221184000 bits/second,
    or 210 MB/sec.

    Memory is a serious constraint for me, as most of the images tend to reside in memory before I get to process them. (and besides, the results go back to a different location in memory...)

    memory BANDWIDTH IS my problem. Latency doesn't effect me much, because its nearly completely sequential reads/writes, nevertheless, this is something that the cache does not cope well with.

    (And I really want to process 4 video-streams at a time, think 840 MB/second...)

  • I haven't had an AMD processor yet I haven't had to underclock to make stable for server use. I stopped using AMD back when the first athlons appeared.
  • I am sure ASUS, and EPOX would be glad to hear you call their products junk. These machines are servers - at the time the only place I cut costs was AMD, because I believed in the product at that time to be equal to intel and less expensive, at the same time. There's nothing but excellent brand name products in these machines - hand picked to be very linux friendly. Now it's Dual Intels all the way. The speeds AMD is reaching is making me want to try them again, but I am reluctant, we had many (6+) machines with problems as such back when the 350's first came out, AMD ignored our questions, all we wanted was some input to help us figure out what it was. I got the same problems with 350's at 350Mhz as I did with trying to overclock a 300 to 350, makes me think AMD just couldn't stand up to the pressure of actually working the CPU.
  • The two of them have been playing "tit-for-tat" for some time now... I wonder how long Intel will be able to keep up that game. Not long, I'd wager. I wouldn't be suprised to find that they have no answer for this. Wilamette might be Intel's answer further down the road, but it is hard to say what with the K8 (and, yes, the K9) looking so nice. About production... That has been AMD's problem for a while. Anyone got any links indicating how well they have been able to meet the demand for K7's?
    Why do you think that Intel will have trouble keeping up with AMD? The Athlon doesn't even have a good chipset yet. There's no SMP, PC133 support was just announced (I don't see any PC133 Athlon motherboards for sale yet), ditto AGP 4X, and the faster Athlons are running the off-die cache at 2/5 speed! It sounds to me that the Athlon has some catching up to do, really. Yeah, the Athlon is pretty fast, but the engineering leaves a little to be desired. I'd really like to see an SMP Athlon motherboard with PC133 support (or DDR SDRAM). There is no Athlon chipset that can even come close to the i840 chipset. Not even close. Try running dual 733 MHz Coppermines on an i840 motherboard. Then compare that to a single CPU 750 or 800 MHz Athlon. The Athlon will get slaughtered. I guarantee it.
  • I don't believe it! A company announces and demo's a fairly major step forward in chip technology - running a really powerful processor as speeds of over 1 Mhz without any fancy cooling systems, and you want to know how fast it'll play a game?

    As mentioned before, the processor is becoming less of a factor in the Quake arena. The bottleneck is memory access times, bus speeds, graphics cards, drive speed, etc. etc.

    Banging one of these things in, rather than say a 700 Mhz Athlon isn't going to make much of a difference to your gameplay....

  • The boards with the VIA KX-133 chipset, which does 133mhz RAM and AGP 4x, are hitting the market this week. You can get them in Japan now, but they may take a few weeks to make it to the states. They are a 4 layer design, so they will actually be cheaper in the long run than the Fester style boards.

    Also, the DDR chipsets should be coming out this summer, which will allow the RAM to run at 266 Mhz, which should be even better.
  • Just an afterthought, but as AMD continues to win the speed war with Intel, one must remember that most people have boards that use Intel chipsets. It could seem feasible that Intel could/will try to further the rift of chipset compatibility when/if AMD contiues to win the speed war. I am somewhat in the dark about topic, so please don't use my ignorance as flame bait.
  • Cache. A big load of on die cache possibly supplemented by a bigger load of not on die cache.

    The other answer is DDR ram, so you can jump from PC 133, to PC266 memory, wooha!

    yes, memory speed is a problem in PC world, but still, upping the MHZ is a good thing, especialyy when you have a sizable cache to work with. Remember back in the days when computer had a mere 640k of memory in TOTAL to work with? Well now we have about the much in cache running at the SAME SPEED as the processor =) which aint such a bad situation really. Clearly a large set of problems can be solved by code that almost totally fits in cache.
  • The AMD-750 chipset doesn't do SMP, and neither does Via's new KX133 chipset -- the chip itself is ready for multiprocessor configurations, but nobody's made it feasible yet, and don't expect it for a while.
  • Well first of all you're confusing bus speed with lack of memory, but I'll only concentrate on bus speed.

    If you think the limitation of slower RAM than processor clock is so horrible that "processor speeds above 400MHz don't make that drastic difference" you obviously don't know much about memory caching technology, or haven't looked at any high speed benchmarks lately.

    Charts such as this one: http://www6.tomshardware.com/cpu/99q3/990823/image s/q2.gif seem to demonstrate that today's modern processors are doing just fine for themselves scaling to high clock rates even though the memory bus is still slow.

    -------------
    The following sentence is true.

  • Re:... and if that pizza gets cold ... (Score:3)

    by mOdQuArK! ( 87332 ) on Tuesday February 08, 2000 @09:43AM (#1296454)
    Heck, you can boil the hot water for your coffee on top of the CPU - then use the CDROM tray as a cup holder!

  • Wherehave you been??? I hate to burst your bubble but don't seem to fully understand what you are talking about.

    . . . This became a serious speed limiter and newer processors added a back-side bus strictly for cache (one reason that the CPU modules appeared.) Back-side bus cache runs around 400 MHz plus three or so bus cycles added latency. At 800 MHz this starts to get ugly.

    Sorry, wrong. Backside bus was implemented to run the cache at a speed faster than the memory bus, but in pc architectures its not fixed at 400MHz. Like every other clock rate in the system, the backside L2 is run at a multiplier of the FSB. In all P-II's, non-CuMine P-III's and Athlons up to 700MHz this is set to 1/2 the CPU multiplier (Athlon 750 is set to 2/5 of cpu because AMD's cache yields are not yet good enough to handle 375MHz). i.e. for a P-II 450 the setup would be:

    • memory clock= FSBx1 = 100MHz
    • CPU = FSBx4.5 = 450MHz
    • L2 cache = CPU/2 = FSBx2.25 = 225MHz
    • AGP = FSBx2/3 = 66MHz
    • PCI = FSBx1/3 = 33 MHz

    For an old P-II 266, the setup would be:

    • memory clock= FSB = 66 MHz
    • CPU = FSBx4 = 266MHz
    • L2 cache = CPU/2 = memoryx2 = 133MHz
    • AGP = FSBx1 = 66MHz
    • PCI = FSBx1/2 = 33 MHz
    Moving the L2 cache on-chip may not let it run much faster (typically CPU/2 or CPU/2.5) but it cuts the pipeline latency, and latency reduction is what cache is all about. Also, being on-chip makes it much less expensive to use wide busses so the L2 could, for instance, transfer an entire cache line to the L1 in a single cycle.

    Again, wrong. Here you are actually thinking about backside bus setups. Moving the cache on-die allows it to be run at the same clock speed as the cpu, just like L1. This is the setup used in Celerons, P-III Coppermines, K6-III/K6-2+'s, and Athlon Thunderbird's.

  • Just as a bit of information on the side, this was shown at the International Solid State Circuits Conference. [sscs.org] This is the yearly brag, boast, watch, learn and schmooz fest organized by the IEEE. It is a prestigious conference so everybody shows of their latest and greatest. Yesterday it was Intel with 1Ghz today it was AMD. It is not like this is in production allready, just guys showing off.

    What I find interesting is that these are made by wafer-steppers from ASM-Lithography [asml.com]. These guys have been leading the way the last couple of years. I wonder how much Intel is being held back by sticking to their current wafer-stepper producer (Canon? or was it Nikon?)
  • First off at the top of the article they state:

    AMD continues to expect first revenues from AMD Athlon family processors produced in Fab 30 utilizing its leading edge HiP6L 0.18 copper interconnect technology at the end of the second quarter of 2000.

    The at the bottom of the article they state:

    Cautionary Statement
    This release contains forward-looking statements, which are made pursuant to the safe harbor provisions of the United States Private Securities Litigation Reform Act of 1995. Forward-looking statements are generally preceded by words such as "plans," "expects," "believes," "anticipates" or "intends." Investors are cautioned that all forward-looking statements in this release involve risks and uncertainty that could cause actual results to differ materially from current expectations.. . .

    Although I think this will be great (when the prices come down) and all, but I get so disillusioned at promised dates (read Intel) that always get missed. I hope they deliver relatively on time so that maybe by summer we'll have a chance to use the newfound speed.

  • Your not the only one. *shug*:(

  • When will AMD get respect? (Score:3)

    by dpilot ( 134227 ) on Tuesday February 08, 2000 @04:09AM (#1296503) Homepage Journal
    With Athlon, AMD has carried the competition to Intel's doorstep. This is the idea. This is what the marketplace is supposed to do. We are supposed to be the beneficiaries.

    So I wonder when mainstream PC makers will quit considering AMD to be the cheapo alternative and realize that, at least for the present, they are the performance leaders.
  • >>(suing overclockers, for example). Complete bullshit. AMD is telling *companies* they can not sell
    overclocked chips.

    AMD doesn't give a shit what you do with the chip when you've bought it.

    See http://www.hardocp.com/articles/amd/oc/amd_oc_opin ion.html for the full story

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