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China

China May Prove Arm Wrong About RISC-V's Role In the Datacenter (theregister.com) 49

Posted by BeauHD from the effects-of-the-trade-war dept.
Arm might not think RISC-V is a threat to its newfound foothold in the datacenter, but growing pressure on Chinese chipmaking could ultimately change that, Forrester Research analyst Glenn O'Donnell tells The Register. From the report: Over the past few years the US has piled on export bans and trade restrictions on Chinese chipmakers in an effort to stall the country's semiconductor industry. This has included barring companies with ties to the Chinese military from purchasing x86 processors and AI kit from the likes of Intel, AMD, and Nvidia. "Because the US-China trade war restricts x86 sales to China, Chinese infrastructure vendors and cloud providers need to adapt to remain in business," O'Donnell said. "They initially pivoted to Arm, but trade restrictions exist there too. Chinese players are showing great interest in RISC-V."

RISC-V provides China with a shortcut around the laborious prospect of developing their own architecture. "Coming up with a whole new architecture is nearly impossible," O'Donnell said. But "a design based on some architecture is very different from the architecture itself." So it should come as no surprise that the majority of RISC-V members are based in China, according to a report published last year. And the country's government-backed Chinese Academy of Sciences is actively developing open source RISC-V performance processors.

Alibaba's T-Head, which is already deploying Arm server processors and smartNICs, is also exploring RISC-V-based platforms. But for now, they're largely limited to edge and IoT appliances. However, O'Donnell emphasizes that there is no technical reason that would prevent someone from developing a server-grade RISC-V chip. "Similar to Arm, many people dismiss RISC-V as underpowered for more demanding applications. They are wrong. Both are architectures, not specific designs. As such, one can design a powerful processor based on either architecture," he said. [...] One of the most attractive things about RISC-V over Softbank-owned Arm is the relatively low cost of building chips based on the tech, especially for highly commoditized use cases like embedded processors, O'Donnell explained. While nowhere as glamorous as something like a server CPU, embedded applications are one of RISC-V's first avenues into the datacenter. [...] These embedded applications are where O'Donnell expects RISC-V will see widespread adoption, including in the datacenter. Whether the open source ISA will rise to the level of Arm or x86 is another matter entirely.
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China May Prove Arm Wrong About RISC-V's Role In the Datacenter More

China May Prove Arm Wrong About RISC-V's Role In the Datacenter

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  • usually I roll my eyes at speculative articles about how China is going to do XY3, cause lets face it they haven't fuckin bothered to yet (other than piss poor sub par copying) RISC V at the moment is not much more than a curiosity at this point so if China wants to get it head out of its ass and actually do some development work they could catch up to 15 years ago pretty quick and go from there

    • Alibaba's T-Head, which is already deploying Arm server processors and smartNICs, is also exploring RISC-V-based platforms. But for now, they're largely limited to edge and IoT appliances. However, O'Donnell emphasizes that there is no technical reason that would prevent someone from developing a server-grade RISC-V chip

      If it was that easy then Loongson (MIPS) would have been doing this years ago. That's an even more ready-to-go architecture then RISC-V and yet it's gone pretty much nowhere outside of small-scale domestic use, so why would RISC-V be any different?

      • Re: (Score:3)

        by AmiMoJo ( 196126 )

        Loongson has produced server grade stuff. Some Chinese supercomputers are MIPS based. It's just that they are not big enough to compete in that space. It's not just a case of designing the chips, they need to get software support and customer support for it in place. Dedicated machines like supercomputers are doable, but mass market servers are a very different proposition.

        It's the same with Via. They have an x86 licence but don't produce high end competitive CPUs because they don't have the resources to de

      • If it was that easy then Loongson (MIPS) would have been doing this years ago. That's an even more ready-to-go architecture then RISC-V and yet it's gone pretty much nowhere outside of small-scale domestic use, so why would RISC-V be any different?

        Even MIPS is moving towards RISC-V [riscv.org]. MIPS got left behind, it was too hard to make it scale up. It has survived in markets where scaling down was a benefit and a lot of MIPS ASM has been passed around between the companies that deal in these low-end products so there were established solutions to common problems. But now low end ARM cores are stupid cheap, and RISC-V is even cheaper, so the only benefit to MIPS is this established domain knowledge which becomes less relevant daily as the same problems get s

  • At least using RISC-V is more legal than the questionable legality of copying MIPS patented intellectual property.

    They've already created a few supercomputers using MIPS32 and MIPS64. [wikipedia.org]

    Why not pivot to RISC-V and avoid all the legal trouble with the MIPS architecture?

    • What legal trouble would that be? I suspect they don't care about that as evidenced by the existing rampant theft of intellectual property.

      China thinks in the longer term. If RISC V offered a long-term competitive advantage, they'd be all over it.

      Best,

      • Re: (Score:2)

        by kriston ( 7886 )

        I was referring to the MIPS patented intellectual property that is still under patent protection.

        I see they have purchased rights to that patented MIPS IP in recent years. Maybe even MIPS64 is too long in the tooth to keep investing in?

        • After millennia of hammering down any nail that sticks out, China lacks the talent to do their own development. The US has the same problem but it's still sufficiently appealing to people in countries with math education that they come here and solve it for us.

    • Re: (Score:2)

      by AmiMoJo ( 196126 )

      MIPS was properly licenced. All this questioning is just anti-China innuendo.

      The real risk here is to ARM. RISC-V could eat into its business quite substantially.

      • Re: (Score:2)

        by kriston ( 7886 )

        There's no anti-China innuendo here.
        In the early days of MIPS "clones" there was at least one patent that the clone makers did not pay into. It had to do with a single instruction that was either worked around or, in some cases, illegally implemented without a license.

        Several years before that patent expired, they did, eventually, pay to use the IP. The fact remains that they should have licensed it from the beginning.

    • China built supercomputers around MIPS because they did have a license to do so. They require about twice as many nodes to get the same performance as other top supercomputers... but they are in fact near the top of the performance list, at least as reported, because they did throw those nodes at it. Whether they can really deliver that performance or are limited somehow is another conversation, but boring anyway since at best they are slow per node.

      OTOH they probably will pivot to RISC-V just because MIPS is gradually waning while RISC-V is ascendant... and will probably in fact finally kill MIPS. MIPS has stayed around this long despite offering inferior performance compared to ARM because it's been cheaper to license, and because you could customize it more freely. RISC-V is superior in both regards, so the only reason for MIPS to continue to exist now is familiarity.

  • Itanic! (Score:4, Funny)

    by alw53 ( 702722 ) on Friday October 07, 2022 @11:19PM (#62948377)
    Maybe we can convince them that Itanium is the hot thing.

  • RISC-V user perspective (Score:3, Interesting)

    by Aighearach ( 97333 ) on Saturday October 08, 2022 @01:08AM (#62948493)

    I love RISC-V. But I'm an embedded engineer. It is great because it cuts reliance on proprietary toolchains and allows innovation from more parties, without requiring as much investment. The capital requirements of the traditional process limits risk-taking and iteration speed. So this is really great.

    And they've made tradeoffs that benefit those use cases; tradeoffs in the instruction set that make it easier to implement. For embedded, this is good; these tradeoffs benefit microcontrollers. You get the benefits of simplified implementation, and you didn't really give anything up.

    But if you're trying to build a powerful application processor, or a server processor, these tradeoffs mean reduced throughput in high performance multithreaded environments. It is not theoretically possible to achieve the same server performance in a RISC-V based server as in an ARM server if you're using a traditional type of motherboard and operating system. Perhaps there is some way to build a new OS paradigm that gets similar performance-per-transistor for that type of workload. But that's a long ways off, and nobody really wants a new OS anyway.

    People just don't understand, without modern branch prediction you can't make a server that is performant on a operations per watt. It will use more power per calculation in a server environment. On a microprocessor, that's not true, and it is competitive.

    • People just don't understand, without modern branch prediction you can't make a server that is performant on a operations per watt

      True. But Linux and Windows is switching lots of that stuff off to stop data-leaks between processes and VM's. It's fast, but it's not safe on machines where users/customers run their own code. Which is what a lot of data-centers provides.

      • Re: (Score:2)

        by dfghjk ( 711126 )

        By "that stuff" you mean branch prediction? Linux and Windows are "switching" branch prediction off?

        "It's fast, but it's not safe on machines where users/customers run their own code."

        It's slightly "not safe" for specific code, and mitigation is an area of active development. Also, "machines where users/customers run their own code" is necessary but not sufficient for there to be a potential problem.

        "Which is what a lot of data-centers provides."

        It's the only place where such a potential threat exists, bu

    • Huh?

      You can bootstrap from the reset vector, up on both MIPS and ARM with the standard GNU tools. I've done it. Many. Many. Times. It is true that things like Keil do offer a lot of magic keywords are there to make your life easier, but they're not technically needed, and that situation is no different on RISC-V.

      RISC-V is an ISA. And a pretty mundane LSA at that.
      There are superscalar RISC-V processors with branch predictors. It'll work just fine as an applications processor.

      • Re: (Score:2)

        by dfghjk ( 711126 )

        Yeah, RISC-V has history as an applications processor.

        The ESP32 family is an example where there are RISC-V point products as well as "proprietary" processor point products. The result? All the same tools, none proprietary. No difference to the end developer that codes in high level languages. Can't expect the OP to know that though, he's just an "Embedded Engineer".

        • OP is a liar, is what they are.
          I literally started my career in tech as an embedded engineer.
          The first job I had was moving from Keil to gcc for ucLinux on an MMU-less Arm.
          That was a little less than 2 decades ago.

          • You can't comprehend the difference between, "I didn't understand what you said" and "you're a liar," so shut the fuck up, moron.

        • I didn't say that, though. So that's the thing. You didn't understand what I said. That should result in questions. But instead of asking questions, or just fucking reading it again, you went off on the blah-blah.

          I wasn't talking about a difference in high-level languages, I was talking about a difference in fucking circuit design, in making the chips. Designing ICs. You know, the think you use an ISA for?!

      • You're just a dipshit that likes to argue, so instead of trying to understand what I was saying, you're trying to misunderstand it, in a narrow sort of hair-splitting way.

        Whereas, actually, what I said is clear. I didn't say any of the things you're arguing with. You just didn't understand, but you argued anyway. Yes, there are RISC-V implementations with branch predictors. It doesn't matter to you; you apparently don't have enough subject knowledge to know what the fuck I even said.

    • Re: (Score:3)

      by dfghjk ( 711126 )

      "It is great because it cuts reliance on proprietary toolchains and allows innovation from more parties, without requiring as much investment."

      Citations please. What "proprietary toolchains" are being referred to and how are "more parties" allowed to "innovate"?

      "Embedded engineers" that design their own processors are rare, if they exist at all, and embedded engineers that use off-the-shelf processors are not reliant on proprietary toolchains and do not benefit from innovation from "more parties", nor does

      • Citations please.

        If you want to have a discussion, that's not the way to achieve it.

        "Embedded engineers" that design their own processors are rare, if they exist at all

        W T F are you talking about? 100% of the new processor models are designed by engineers. Why are you inserting this "their own" nonsense, and then stumbling over it?

        And then you go on to blather on and on about how you don't understand any of the discussion. You're such a moron, you can't comprehend that design paradigms exist. You're so stuck in Dilbert-land that you can't comprehend having a discussion with somebody who knows how a mothe

        • You get caught lying your ass off, pretending to be something you're not- and you try to drive that home by failing to refute any of his refutations, instead telling him that his demand for citations is not the way to have a discussion, accusing him for blathering for correctly pointing out that EEs don't design CPUs, and then calling him 2 more names on top of it.

          Man, you're so fucking busted. Give it up, dude.

          • Wow, you're really stupid. You either don't know what the "lie" means, or... you're lying. I see you replied 5 different comments I made. You're too stupid to talk to, so I'm not going to read them.

            • Get the fuck out of here with the necro.

              You lied, own it.
              Let's assess.

              I love RISC-V. But I'm an embedded engineer. It is great because it cuts reliance on proprietary toolchains and allows innovation from more parties, without requiring as much investment. The capital requirements of the traditional process limits risk-taking and iteration speed. So this is really great.

              Cuts reliance? Name a competing microarchitecture that relies on proprietary toolchains.
              Lie #1.

              And they've made tradeoffs that benefit those use cases; tradeoffs in the instruction set that make it easier to implement. For embedded, this is good; these tradeoffs benefit microcontrollers. You get the benefits of simplified implementation, and you didn't really give anything up.

              Name such a tradeoff.
              Lie #2.

              But if you're trying to build a powerful application processor, or a server processor, these tradeoffs mean reduced throughput in high performance multithreaded environments.

              Name one aspect of RISC-V that leads to this.
              Lie #3.

              It is not theoretically possible to achieve the same server performance in a RISC-V based server as in an ARM server if you're using a traditional type of motherboard and operating system.

              So fucking laughable. Let us all know how, precisely, the RISC-V ISA precludes the performance of an ARM using "a traditional type of motherboard and operating system".
              Lie #4.

              Perhaps there is some way to build a new OS paradigm that gets similar performance-per-transistor for that type of workload.

              Meaningless jargon inserted to make you sound intelligent.
              No evidence, or even sound

              • You can't even read LOL

                I told you, you can't be talked to. I'm not reading any of that. I already know, you don't know what I said. You don't know what my points were. You can't argue with them. You're not intelligent enough to figure out what I meant before trying to argue, so you fail.

                You want to know why RISC-V can't be as efficient for high-throughput designs, that just means you don't have the subject-matter knowledge to argue with me. I'm an embedded engineer. I design circuits around RISC-V and A

                • Unlike you, I started my career in tech as an actual embedded engineer, with a CS degree.
                  I cut my chops porting kernels to new and exciting architectures.

                  What I want to know, is what the fuck made you think you could bullshit your way through this on slashdot? I mean there was a 100% chance that you ran into someone who actually did it for a living.

                  You did read what I wrote, and we both know it. And as we also both know, you can't answer any single one of my allegations, because you were lying.
                  You're

  • Really? Impossible? (Score:4, Informative)

    by Maury Markowitz ( 452832 ) on Saturday October 08, 2022 @08:40AM (#62948917) Homepage

    > Coming up with a whole new architecture is nearly impossible

    Except for the fact that the two chips in this article both did that.

    Arm did it in the 1980s with a team of about four (five?) people. They decided to do so after seeing that WDC consisted of two adults and some high school students using Apple IIs and hand-cut rubylith, Arm updated that to use BBC Micros and digital layout to produce a ~23,000 gate design that worked the first time.

    RISC-V was developed at UC Berkeley, who had also developed the original RISC which morphed into SPARC. The RISC-V team included Patterson, one of the original RISC developers. They built the entire concept using super-automated tools on systems with infinity power compared to the BBC.

    There's the issue of the "whole enchilada", as opposed to just the processor or ISA itself. That too is infinitely easier today because the two target toolchains you might be interested in are both open-source and designed from the start for cross-platform support. GCC already supports any number of esoteric designs (like the Chinese MIPS-a-like) and designers add their own layers all the time.

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