Design Philosophy of the IBM PowerPC 970

D.J. Hodge writes "Ars Technica has a very detailed article on the PowerPC 970 up that places the CPU in relation to other desktop CPU offerings, including the G4 and the P4. I think this gets at what IBM is doing: 'If the P4 takes a narrow and deep approach to performance and the G4e takes a wide and shallow approach, the 970's approach could be characterized as wide and deep. In other words, the 970 wants to have it both ways: an extremely wide execution core and a 16-stage (integer) pipeline that, while not as deep as the P4's, is nonetheless built for speed.'"

What is: 2H03?

[Malc]

When will the "projected 2H03 release date" be? I'm not familiar with this term.

Re:What is: 2H03?

[ajakk]

Second half of 2003.

Re:What is: 2H03?

[TheViffer]

2h = second half
03 = 2003

In the case of Blizzard that means Fall 2005.

Re:What is: 2H03?

[teamhasnoi]

In the case of Duke Nukem' Forever, that means just after our sun expands to a red giant and swallows the earth and moon.

Re:What is: 2H03?

[Montreal Geek]

That would be the second half of 2003, I.e.: somewhere late in 2004. :) -- MG

Re:What is: 2H03?

[FreeLinux]

Second half 2003. Which almost always slips so the real meaning is assumed to be Q403(4th quarter 2003) or even Q104(First quarter 2004).

Re:What is: 2H03?

[mholt108]

It means to finger the 2nd fret and then hammer onto the third -- duh!

It's got nothing on the Pentium 4

[tcd004]

As evidenced by this review [lostbrain.com]

tcd004

IBM Chip

[MadocGwyn]

Is this not the chip that was a co venture between apple and ibm? Is this also no the chip that apple intended to use? is this also not the chip thats a 'pc' chip built on RISC? Personally I wanna see what this thing can do before damming it or pronounceing apple dead. Its a year from now, the specs could be COMPLETLY different by then

Re:IBM Chip

[MadocGwyn]

How is this a troll might I ask? Story my info comes from is here, as well as present article Here/a [slashdot.org]

Re:IBM Chip

[Hast]

It's a scaled down version of the Power4 CPU which IBM use in their mainframes. It's also been designed to be compatible with Motorolas AltiVec vector processing.

It's very likely that Apple intend to use it in future high end boxes. (They would be rather stupid not to.) Unless Motorola can one-up IBM by then.

I don't think it has all that much to do with Apples future though. Apple boxes have not really been about high performance lately, and people buy them anyways. Mostly becuase they like the OS/apps and such I assume.

And the specs are pretty much solid now I assume. Creating hardware is /very/ different from software were you can update and patch it to the last minute. They might be able to tweak the clocks a bit, but don't expect a lot more.

Question

[wcbrown]

What's the difference between the Power4 and the PowerPC 970? As a Mac guy, I've been following all of the rumors and announcements with interest but I keep seeing the PPC970 referred to as a scaled-back version of the Power4.

Why wouldn't Apple go with the Power4 over the PPC970? And I already know that nothing official has been announced by Apple and that this is all probably going to be a lot of sturm und drang signifying nothing, but that's what keeps us Mac guys going I guess.

Re:Question

[Faggot]

The PowerPC 970's design is adapted from IBM's successful Power4 server processor. Physically smaller, the PowerPC 970 sacrifices some execution units -- including the Power4's second processor core -- for 64-bit compatibility and the SIMD unit.

While the Power4 core has two processor cores and massive caches for MP implementations, the PowerPC 970 has only one processor core, an SIMD unit and a 512K on-die L2 cache. The cache includes error correction. The PowerPC 970, as described today, has no connectors for an L3 cache.

Re:Question

[mfago]

the PowerPC 970 sacrifices some execution units -- including the Power4's second processor core -- for 64-bit compatibility and the SIMD unit.

This implies that the Power4 is not 64 bit -- which is of course wrong.

I would say that the PowerPC 970 trades the second core and fancier interconnects of the Power4 for lower power, cost, and the SIMD unit.

Re:Question

[alannon]

My guess was that he meant "for 32-bit compatability". As far as I know, the Power4 is not binary-compatable with 32-bit PPC executables. IBM would be foolish to release a DESKTOP PowerPC chip that was off-the-bat incompatable with all current software made for Apple's brand new OSX.

Re:Question

[Zueski]

Actually, its based on the Book-E standard, same as the 601, 603, 604, G3, G4, etc. So, assuming all the execution units are present (i.e., AltiVec), it should run the same code. Book-E is a 64 bit archetechure that can be implemented as a 32 bit version.

Re:Question

[mfago]

the Power4 is not binary-compatable with 32-bit PPC

As long as you don't compile with -arch=pwr4 (etc), xlc (IBM's C compiler) will compile the code to run on any Power or PowerPC.

Re:Question

[afidel]

No, the PPC970 loses a number of execution types (read the recently linked article about the POWER architecture in contrast with PPC), the second core and the extremely large cache of the Power4 and gains SIMD and lower power usage. Basically it's a desktop cpu instead of a big iron cpu.

Re:Question IT IS ONLY 40 BITS not 64.

[Anonymous Coward]

IT IS ONLY 40 BITS not 64

Your desire to use address pins (or is it max pinned space per process?) to measure size puts you in a distinct minority. That doesn't make you wrong. But neither does it help make you right in this particular jungle.

Systems whose physical addressing match their claimed "bitness" are probably in the minority.
Some systems provide more physical addressing than register width (later PDP-11s, 8086, S/390), some less (68000, classic CDCs, early POWER). The 970 falls into the less category. Nothing unusual there.

Apple, like EVERY OTHER OS KNOWN, will steal a bit or two

Some bits come from physical addresses, some from virtual addresses. These should be addressed [pun slipped in, sorry] separately. AIX, btw, steals less than one bit. Linux can also be configured to steal less than one bit. (Assertions I can get away with no loss of credibility, since AC's have none to start with.) Were you frightened by a VAX in your formative years?

Why do fanboys mod stuff like this down?

Because we can't figure out why someone who needs 512GB, or 1TB, or more (which is it?) cares that a Linux process is limited to 1GB and not 2GB or 4GB.

Re:Question IT IS ONLY 40 BITS not 64.

[Anonymous Coward]

40 bit address bus. Not a 40 bit data bus. BIG difference there.

And the 40 bit address bus is most likely a pin packaging limitation. They did not see a need to bring those extra 24 address lines out to the chip package. Internally, it is 64 bit. Much like the venerable MC68000 was 24 bit externally, but 32 bit internally.

But seriously, in the life-span of THIS processor implementation - do you seriously see ANY desktop manufacturer even thinking about putting that much RAM in their CPUs?? Heck 1GB of RAM is not 'standard' yet. Extrapolating w/ Moore's Law, we'll be approaching 40bits in 8 years. Apple will undoubtedly have another chip before then!

If you truly need THAT much physical storage today, you'll need to shell out for a SERIOUSLY large server. IBM's high-end p690 currently maxes out at 256GB. The virtual address space is undoubtedly much higher.

Tom

Using Big RAM in the Real World

[billstewart]

There are several different limits you'll encounter, which will have different effects on the programs you write as well as on the machines you can afford to use...:

• Physical RAM limits - at ~$100/GB, commercial applications can easily afford a TB of RAM, but it's not that simple putting it into one computer - with 4GB RAM boards, that's 256 boards, which won't fit on your average PC ATX motherboard.... Solid-state disks can do the job, with obvious differences in performance from RAM or cache, but they usually lead the CPU-memory market by a couple of years. By the time you can get a normal machine with 1TB of RAM, that Power4/970 will be an antique, and you'll be complaining about the lame 48 bits in your wristwatch's address space.
  
• Virtual Address space you can mmap() or put in a single array - this makes a lot more difference, because it affects whether your programs can view the large space as a segmented or unsegmented thing, and whether you need visibility into the memory structure, and whether you can get the visibility if you want it. For most scientific applications, it's not a big deal, because you seldom need it all in a big 1-D array; more commonly, anything that needs a huge address space is working in 2-D or 3-D, so you run an ugly setup thing to get your array pointers initialized and then return to normal programming.
  
• Virtual memory for files and databases, though, is more of a problem. It's convenient to be able to treat the disk as one big flat virtual array, even if you do a certain amount of explicit management on the relationship of disk and RAM rather than leaving it all up to the VM system. A terabyte of disk is under $2K these days, though if you want faster disks and faster busses you might pay a bit more, but the costs of disk have been diving faster than CPUs for a few years, and anything below about 47 bits of address space for disk starts to heavily eat into the programming effort for products that are meant to work for a few years.

Almost two decades ago, I was supporting a network modelling application that needed 12MB, and our computer was a VAX with 4MB of RAM, but fortunately 4.1BSD and System 5.2p were able to give it enough virtual memory to scrape along. Our typical runs took about a week, until a couple years later when the price of RAM dropped to the point that we could afford to upgrade to 16MB, at which time it dropped to an hour per run.

One thing we found out was that as you approach the limits of a machine's capacity, all the details of the architecture that you were able to ignore on smaller problems become visible, like how the TLBs work and what the memory page sizes are; things became somewhat clunky at 6MB and much more clunky at 22MB (or maybe 24MB), and some of that may have been the OS rather than the hardware. The extra 12MB RAM cost us approximately one person-year's salary, but unfortunately corporate accounting rules made it much harder to buy capital equipment than to make our study take a year longer.

At this point, I'm supposed to include the obligatory old-geezer rant about walking to the mainframe, five miles in the snow, uphill both ways, carrying punch-cards and hand-winding magtape, but that was back when I was an undergrad, and we didn't actually go to the mainframe, just the card-reader/printer/keypunch room which was half a mile away (still snow and hills), and the reason I handwound the magtape was because the professor's only copy had a cracked reel, though we did use hand-cranked papertape tools to do it, and I really _did_ wind papertapes by hand :-)

I haven't dealt with these problems lately - Moore's Law has long passed the limits of any problems I solve in practice, laptop diskdrive sizes have gotten two jumps ahead of Microsoft bloatware (though fitting backups onto CD-Rs feels a lot like fitting them onto floppies used to), and the only practical application I've got that could think about pushing the terabyte disk boundary is Tivo, if I'm willing to devote that much resources to something that makes me watch more television... The reason it took so long to get the 120GB drive on my 233MHz Pentium wasn't cost, it was BIOS upgrades :-), and if I decide to rip all my CDs onto the disk, it'll mainly be just because I can.

Re:No connectors for L3 cache?

[Lars T.]

Uhh. Cache (SRAM) has far lower latency than DRAM. IOW you already have the data from cache when your RAM hasn't started sending it yet.

Re:Question

[WatertonMan]

As for why Apple wouldn't go for the Power4, it is because it simply is too expensive. Further Apple wants something like the Altivect unit that is in current G4s. Power4 is simply optimized for non-desktop uses and is overkill for what Apple needs. The 970 is a nice balance between Apple's needs and the Power core. Further by moving to IBM Apple is able to get a far better provider than Motorola whose G5 has been missing in action for some time now.

Re:Power4 vs PowerPC 970

[NattyDread]

The other responses to your question have pretty much hit it dead-on. I just wanted to comment that the PowerPC has always been the little brother of the Power architecture used originally in the RS6000 ... and now in almost everything IBM makes - AS400, E9000, etc.

The first generations (601, 603/604 and the ?aborted? 620) of the PowerPC line were scaled-back versions of the Power and Power2 architectures respectively [the original Power architecture was mounted on a 3x5 daughter card with 4-5 separate chips [I'll have to go looking for my tech papers] making-up the core ... because of this the migration of everything into one die for the PowerPC was amazing.

Additionally, IBM has tended to work-out new capabilities -- such as the move to 64-bit and dual cores -- on the larger scale Power architecture, before attempting to stuff it into the smaller PowerPC pacakge [besides, IBM has to keep something to distinguish its pricier iron from the OEMs. ;)

Natty

Re:Power4 vs PowerPC 970

[chrysrobyn]

The first generations (601, 603/604 and the ?aborted? 620) of the PowerPC line were scaled-back versions of the Power and Power2 architectures respectively [the original Power architecture was mounted on a 3x5 daughter card with 4-5 separate chips [I'll have to go looking for my tech papers] making-up the core ... because of this the migration of everything into one die for the PowerPC was amazing.

The PowerPC 601 was not a scaled back version of the Power series. To say this would imply that they took the design and modified it. In fact, they took the Power instruction set, modified that and then designed the processor to support it for the target markets.

The 64 bit PowerPC 620 was not "aborted" per se (like the PowerPC 615 was), rather IBM decided that its role was filled by the higher clocked 604 series and the then soon-to-come IBM Rochester, MN designed 64 bit PowerPC 630 (aka Power 3).

To verify my claim that the PowerPC 620 was not aborted, Motorola got suckered into manufacturing [kegel.com] them for Bull [club-internet.fr].

Re:Question

[Coz]

Another reason (in addition to the excellent ones other folks have listed) - cost. Power4 chips are over-engineered, compared with "consumer" CPUs like the G4, P4, and 970. Hannibal's article mentions that at the same clock speed, some instructions execute faster on the 970 simple because of the thickness of the oxide layers used in the transistor gates. It's a different emphasis - high reliability and expense versus "less" (still acceptable to 80% of the world) reliability and acceptable mass-production cost-per-chip.

Plus, the Power4 is really designed as a server/Big Iron chip - it's really 2 CPUs on 1 die - and that's just not what an iMac needs.

Re:Question

[Shuh]

Putting two CPU cores on a single die is also more costly, as you are basically doubling your failure rates. So if you were tossing out 5-10% of dies when they were single-core due to defects, it's within the realm of possibility that you'll need to scrap 10-15% of your dual-core dies, ceteris paribus.

But if they did their design right, they wouldn't have to have a dual-core and a single-core fab. They would just be able to cut the dead/slow die off the good one and sell it as a single, or else disable one and mount it in the same package and sell it as a single.

Re:Question

[mfago]

The reason that Apple won't use the Power4:

It is HUGE [com.com].

The picture at the top right shows the Power4 multichip module as used in the p690. Yes, it is the 5" square thing in the guys hand.

There are better pictures of the MCM itself, but I couldn't find the close-up showing just the MCM in someone's hand.

The large size (along with everything it entails: it uses 125W power, and supposedly costs about $3500 to manufacture) is one indication that IBM designed the Power4 for its big-iron. Nevermind that IBM does offer the Power4 (sans MCM) in some of their smaller servers.

The PowerPC970 is the equivalent processor tweaked for the desktop/low-end servers.

Re:Question

[Billly Gates]

As evident in the article, the transistors and logic gates in the power4 are biger and alot more expensive to produce to increase reliability. This is not needed in a desktop and it slows down performance since the gates can't switch as fast. I find this claim hard to believe since any freebsd and linux (2.2 and earlier kernels) can run for months and years without a single reboot.

The power4 costs 4-5k per cpu. Obviously too expensive for desktop systems because of high end server features and very large caches in the chip that will offer no performance benefit to desktop apps. Only heavily threaded multitasking apps running in parrallel will see the performance improvments by a power4. A web server running servlets and databases are the examples I refer to as heavily threaded multitasking applications. Adobe photoshop will show little performance difference and may even run slower on a power4 vs a powerpc 970 due to the lack of simd instructions.

IBM did good with this processor and its leaps and bounds ahead of the g4. The main limitation of the g4 is the lack of ddr memory support. In ddr macs the chipset has to slow down memory access to the cpu to 133mhz speeds and it creates a very serious bottleneck. This alone is bottlneckintgthe processor down to half its potential in +1 ghz processors. Expect a %200-300 performance increase with these new processors.

Re:Question

[ealar dlanvuli]

Basically it can be sumed up that the PowerPC 970 is a Power4 minus some "server perks" and manufactured with desktop level reliability in mind (everything becomes majorly cheaper when your chip can stop doing self diagnostics and chips failing in 5 years is slightly acceptable).

They have a slightly divergent instruction set, but considering neither actually perform the instructions they "support" that's not anything worth noting.

An overview of pipelining

[PhysicsScholar]

Some of you may have read an extremely wide execution core and a 16-stage (integer) pipeline in this article's write-up and been extremely confused. I took a few computer architecture courses back in my undergrad days, so I can refresh some of your memories as well as teach basic processor design to those of you who never got to attend a 4-year college and study computer chips in-depth.

Basically, all modern processors are pipelined. This means that they execute various instructions at the same time. Whereas doing a load of wash, waiting for it to finish, putting it into the dryer, waiting to finish, and then folding would take 30 minutes * 3 steps * 3 loads = 4.5 hours, one could PIPELINE such a process, thus removing sequentialism and doing the first load, then while that's drying put the second load into the washer, and so on ... this takes a much shorter amount of time.

This is all a processor really does. It does a FETCH, an INSTRUCTION DECODE, then an EXECUTION, then perhaps a MEMORY READ/WRITE, and then a WRITE BACK, perhaps. So this 16-stage pipeline can have 16 different instructions executed all at the same time, but just in different points of its execution. The example in CAPS above is a 5-stage pipeline that's similar to those in MIPS processors.

Hope this was helpful!

Re:An overview of pipelining

[lamp77]

Your not doing my laundry with that kind of attitude!

Re:An overview of pipelining

[joto]

Hope this was helpful!

It wasn't. You only explained "deep", not "wide". Since both words occured in the sentence you were trying to explain, you should try to do better than only explaining the one you remembered from college...

Re:An overview of pipelining

[LumpishGenius]

It's bona-fide. Even when he trolls he's usually more right-on than 99% of posters; in this case it's 100% informative, no bullshit.

For a decent intro to pipelining, Google for design notes for the MC6502, the first pipelined processor.

$$$/performance

[teamhasnoi]

That's what I want to see, and missing in the article and links. Anyone have an idea?

I recall IBM's PPC boards going for over a grand, which is (to me) far too much. Especially when it was a 'G3' chip.

Even if the new chip is faster, will I be able to buy 2 pentium 4's (5?) for the price of it?

What?

[mill5ja]

How on earth is anyone supposed to know what this part is going to be priced at? I doubt IBM even has anything resembling a firm idea. The price is going to depend on yields, production quantities and a number of other factors.

-jason m

Re:$$$/performance

[Anonymous Coward]

Were you by chance looking at PowerPC evaluation boards? Those are low-volume boards intended for prototype developers only and thus, somewhat more expensive than high volume boards.

Tom

Die size as an indicator of cost

[IIci]

Looking purely at die size, one can expect manufacturing costs of the p4 and ppc970 as being roughly equal: PowerPC 970 1.8 GHz, 0.13um, 121 mm2, 52 million transitors Pentium 4 2.8 GHz, 0.13um, 131 mm2, 55 million transistors As long as IBM is not using the exotic materials of the power4, then the main advantage Intel has for pricing is that their R&D can be spread over many more chips. What the R&D costs of the ppc 970 are is interesting, especially since IBM is trying to position themselves as a maker of custom chips leveraging their ppc ISA and the experience gained through their big bucks power series.

Every time I readone of these articles...

[larien]

...I realise just how little I know.

Kudos to the Ars team yet again for going deeper into CPU designs than 99% of the populace need to go :)

Re:Every time I readone of these articles...

[selderrr]

Kudos to the Ars team yet again for going deeper into CPU designs than 99% of the populace need to go :)

lol... did anyone else read an 'e' too many here ? Surely smells of goatse that way :-):-)

Re:Every time I readone of these articles...

[renoX]

If you want to learn more about CPU architecture trade-off, the best book I know is "Computer Architecture: A Quantitative Approach"
by Hennesy-Patterson.

A really good book, not too hard to read..

Comparison without AMD?

[rsborg]

I think that since this is a 64 bit chip, why not compare it with other 64 bit consumer desktop chips (ie, AMD Clawhammer)? A lot of Intel's questionable moves (12K micro-ops instruction cache?) for the P4 were obviously not copied by AMD, and x86-64 seems to be the 64 bit desktop chip of the future.

Re:Comparison without AMD?

[toddhisattva]

RTFA - Hannibal says why he wrote these comparisons and not vs. Hammer, SPARC, Alpha....

Re:Comparison without AMD?

[Coz]

The article points out that a comparison with the AMD chip would be appropriate, but it's not "out there" right now as a basis for comparison. Hannibal says he'll probably use the 970 as a reference when he gets hold of the Opteron and does his down-in-the-registers review of it.

Decoded cache in the P4.

[Christopher Thomas]

A lot of Intel's questionable moves (12K micro-ops instruction cache?) for the P4 were obviously not copied by AMD, and x86-64 seems to be the 64 bit desktop chip of the future.

The P4 has its flaws, but IMO cacheing decoded instructions isn't one of them. It shortens the pipeline, and paves the way for a true trace cache (cache of decoded basic blocks indexed by entry point; very handy for renaming and scheduling).

Whoa

[MalleusEBHC]

The PowerPC 970 has other potential customers as well, though, not the least of which is IBM itself who, with its large investments in Linux, would love to see a high-performance, 970-based 4-way or 8-way SMP Linux desktop workstation halt the steady flow of former 64-bit *NIX workstation users who began switching to Wintel hardware in the late 90's.

Before all my fellow Mac users start A) thinking about going to Linux B) drooling C) wondering about Darwin or D) some combination of the above, let me remind you that Darwin scales very well. You can now return to your previous state of awe.

PS - How much you want to bet good ol Steve is already having wet dreams about doing the traditional Photoshop test at a Macworld with 4-way SMP?

PPC, not just for Apple any more

[d3xt3r]

One of the more interesting, non-technical observations made by the author is that IBM most likely has some real consumer products in mind for this chip, not just helping Apple replace it's G4's.

"The PowerPC 970 has other potential customers as well, though, not the least of which is IBM itself who, with its large investments in Linux, would love to see a high-performance, 970-based 4-way or 8-way SMP Linux desktop workstation..."

This chip could be the start of something big in the Linux space as well. Think about it, we are now at a point where a few companies other than Intel are now poised to take the center stage in the next gen workstation, most notably AMD, Apple, and now IBM themselves.

While Linux has run on PPC chips for a long time, it is difficult to come upon a G4 chip without paying the "Apple Tax" for the hardware. If IBM steps up to the plate with this chip, which can then run OS X, Mach, Linux, *BSD, (insert other OS'es here), and can be purchased directly or in a package from IBM, we may see a good set of Windows challengers for the desktop and server room. Obviously OS X will still only run on Apple derivatives.

These chips will be big, I guarantee it, and not just for Apple. It will be interesting to see if Microsoft ports Win XP to these chips.

Re:PPC, not just for Apple any more

[Drakonian]

PowerPC hasn't been just for Apple for quite some time, as evidenced by the 3930 hits for "Embedded PowerPC" on Google or the Embedded PowerPC Resources and Information [go-ecs.com] page.

Re:PPC, not just for Apple any more

[Elwood P Dowd]

These chips will be big, I guarantee it, and not just for Apple.

Don't guarantee it 'till you see the prices for the chips. The G4 is pretty expensive.

Re:PPC, not just for Apple any more

[Sloppy]

That sounds a lot like the Open-WhateverItWasCalled that IBM/Apple/Motorola were promising a decade ago. We'll run Taligent and OS/2 and Unix and NT and MacOS on it.

Hey, I'll be delighted if it really happens, but that sounds like the usual "BIG NEWS in two weeks" type of stuff from my Amiga days. I can't believe it anymore, and if I tried, I would go insane. Mock my unrealistic fanboy idealism once, shame on you. Mock it twice, shame on me.

Re:PPC, not just for Apple any more

[Christopher Thomas]

This chip could be the start of something big in the Linux space as well. Think about it, we are now at a point where a few companies other than Intel are now poised to take the center stage in the next gen workstation, most notably AMD, Apple, and now IBM themselves.


Bear in mind that when IBM says "desktop workstation" they mean a $20k+ machine. Consumer desktop machines these aren't.

built for speed

[selderrr]

sigh

A deep pipeline has as much to do with speed as the number of characters in the processors name. Deep pipelines allow for higher MHz. That's all there's about it. Granted, for two processors of the same architacture, the one with higher MHz is faster. But you can't claim a CPU to be built for speed solely based on it's pipeline depth.

UUUUUUUUUH I hate explaining this shit, but my god /. editors have such brainfarts lately I just had to say something.

Re:built for speed

[p4ul13]

I'm impressed that we've gotten this many posts, and as far as I can tell I'm the first person immature enough to say something along the lines of "huh huh, deep and wide huh huh".

Yeah, sorry.

Re:built for speed

[fobef]

Actually there is quite a lot of research on what the optimal pipeline depth is for a processor, and for an x86 manufactured with a modern process, the conclusion seems to be that a pipeline of between 40 and 50 stages would be the optimal, given that enough resources could be devoted to the design of it.

If you're interested, take a look at the following documents (you might wanna check the urls for spaces):

http://systems.cs.colorado.edu/ISCA2002/FinalPap er s/Deep%20Pipes.pdf

http://systems.cs.colorado.edu/ISCA2002/FinalPap er s/hartsteina_optimum_pipeline_color.pdf

http://systems.cs.colorado.edu/ISCA2002/FinalPap er s/hrishikeshm_optimal_revised.ps

very deep pipelines

[Christopher Thomas]

Actually there is quite a lot of research on what the optimal pipeline depth is for a processor, and for an x86 manufactured with a modern process, the conclusion seems to be that a pipeline of between 40 and 50 stages would be the optimal, given that enough resources could be devoted to the design of it.

If you're interested, take a look at the following documents (you might wanna check the urls for spaces):

What makes me leery of taking these results at face value is that the performance peak is very broad (i.e. incremental benefit is low beyond a certain point), while the first paper, at least, seemed to gloss over a few important concerns (keeping clock skew and jitter very low when distributing to that many more stages, increasing overhead from the bypassing network, etc).

Still an interesting set of papers, but I'm not (yet) convinced.

Re:very deep pipelines

[bmajik]

asynchronus logic might mitigate clock propagation, and have added benefit of avoiding latch delay
(which becomes a more and more significant overall factor as k and f go up...)

i think i saw at least one cpu where latch delay per stage was equivalent to stage-execute time.

the biggest reason im skeptical of deep pipelines is that they suck unless the instruction mix is hand picked. in nature, 30% of instructions are branches. compilers can only do so much to lengthen the basic block, and predictors can only be right "most" of the time.

Holy B-Jesus!

[Smirks]

I've read the intro up there 4 times and I still have no clue what it says! Is this some kind of secret code for Al Qaida?

Understanding 64-Bit Processing

[flux4]

David Every has a great article [igeek.com] about 64-bit processors (referencing the IBM 970, although not by name) over at iGeek.com. Includes an interesting look back at Motorola vs. Intel over the years, and talks about how 64-bit addressing can reference about 18.5 quintillion (18,500,000,000,000,000,000) memory bits, for 16 Exobytes of memory. That should do us for a good while.

Re:Understanding 64-Bit Processing

[MyHair]

. . . 64-bit addressing can reference about 18.5 quintillion (18,500,000,000,000,000,000) memory bits, for 16 Exobytes of memory. That should do us for a good while.

No one will ever need more than that.

Re:Understanding 64-Bit Processing

[benedict]

And of course we'll be making computers out
of silicon til the end of time, right?

Re:Understanding 64-Bit Processing

[seanw]

no, dude, I'm alraedy using liek at LEAST 2 solor masses of silicon in my boxen

Re:Understanding 64-Bit Processing

[NeoSkandranon]

640 exabytes should be enough for anyone...

wide / transistors

[Sebastopol]

it operates very much like itanium, w.r.t to group bundling / dispatch of IOPs. Very much like itaniums 3-bundle EPIC codes, but itanium requires the compiler to best pack the templates, whereas the 970 builds each bundle based on dependencies. funny how they both punt with nops.

i wouldn't be surprised if it has similar int performance as itanium, but better fp. i would expect integer to be better on p4 by the time the 970 hits the streets in systems. intel keeps increasing the number of int execution ports.

although, i wouldn't call it wide-and-deep -- it has distinct vector and FP units, but they are rarely used simulataneously, so i suspect they will be idle most of the time. there's only 2 integer units compared to p4's 4.5. so if most of the time the execution engines are idle, it isn't really 'wide'.

goes to show how bulky x86 decode is -- 970 has fewer transistors, but the same cache size, more branch resources, and more Vector/FP hardware than p4!!

now watch the bias on /. as the same people who praise the wide-and-deep tradeoff of the 970 are the same ones who fault the p4 for 'running at a high-clock speeds but not really doing anything'.

Re:wide / transistors

[dke]

This is a little like EPIC; except that bundling 5 instructions (IOP's), is bigger than 3.

And VLIW (even EPIC) requires the compiler to adapt the code to the hardware. The 970 uses hardware to adapt the software to match it's needs. A next generation version could have 10 units, and the software wouldn't be optimized for 3 instruction bundles (like EPIC), etc....

Also, while there are more int units in the P4, my understanding is they are not all full units. And in the 970 case, you were ignoring that the vector unit is a better int unit for most things than the Int unit (and it has 2 more ALU's, that are actually up to 16 separate ALU's each).

The point is that if I'm doing int calculations or moves, then the AltiVec unit is much better than the Int units in the P4. So the only thing the 2 int units in the 970 should be used for is address calculations, branches and a few scalars that don't fit the vectors.

Re:wide / transistors

[Sebastopol]

Also, while there are more int units in the P4, my understanding is they are not all full units. And in the 970 case, you were ignoring that the vector unit is a better int unit for most things than the Int unit (and it has 2 more ALU's, that are actually up to 16 separate ALU's each).

Ah, I see. I was associating "vector" with packed floating point, and completely forgot about vector integer.

But doesn't that depend on the compiler? Would it dispatch any integer op to the vector engine, or is there a way for the 970 to know if an instruction is an address calculation via a special opcode? Otherwise you again have the problem of compiler dependency like Itanium.

Re:wide / transistors

[Hannibal_Ars]

it operates very much like itanium, w.r.t to group bundling / dispatch of IOPs. Very much like itaniums 3-bundle EPIC codes, but itanium requires the compiler to best pack the templates, whereas the 970 builds each bundle based on dependencies. funny how they both punt with nops.

This is a common misconception, probably stemming from some early coverage of the Power4 by Keith Dieffendorff(sp?) where he for some unknown reason called the Power4's instruction bundles "VLIW-like". The problem is that the bundles are strictly in program order. There is no dependency checking or code scheduling that goes on in the building of these bundles. They're built along completely different rules than bundles in a VLIW machine.

All the out-of-order stuff happens in the back end, in the scheduling queues, just like on any other non-VLIW processor.

Wide, Deep and Built for Speed

[burgburgburg]

So let me get this straight: Is this tech pr0n?

Wide and Deep - Hail Mary pass perhaps?

[twoslice]

In football (the oblong ball not the round one) going wide and deep is sometimes referred to as the hail mary pass. Just like a hail mary pass, If IBM succeeds it will look brilliant, otherwise it will look like a futile attempt to score a winning TD in the war of the processors.

if....

[hikeran]

If IBM were to use these in their own desktops rather than Intell's .. would they hit the same wall/resistance from the ignorant crowd that buys pc's .. (amd 900 must be slower than that intel p3/1000 due to the number being lower?) Or would it be like those old cyrix winchips? god i hated those things..

G5?

[gouldtj]

I know that the press believes that Apple is going to grab IBM's chip hot off the presses, but does anybody know anything hard core about Motorola's G5?

Re:G5?

[Sycraft-fu]

Go look on their site, they have specs on the first of their G5 chips:

http://e-www.motorola.com/webapp/sps/site/prod_s um mary.jsp?code=MPC8540&nodeId=01M98655

Re:G5?

[Lars T.]

Wrong [motorola.com].

Finally, my girlfriend can be happy

[ndogg]

When I had the Pentium 4, she complained about its narrowness, but its was great. With the G4 Mac, it was nicely wide, but too short, she would note. I'm sure that with the 970, I can fulfill all her dreams!

For those /.ers who will not read the article

[Sivar]

...an extremely wide execution core and a 16-stage (integer) pipeline that, while not as deep as the P4's, is nonetheless built for speed.

For those not planning to read the article, I wanted to mention the following so you do not get the wrong impression. The speed that the article refers to (of a long integer pipeline, like a 16-stage or like the Pentium IV's 20-stage) is clockspeed, not necessarily actual performance. The P4's super long pipeline, for example, allows it to run at higher clock speeds, but less work gets done in the same number of clock cycles. This is the "braniac" vs "speed demon" philosophy (with a high clock speed but low instructions-per-clock representing "speed demon") and neither is necessarily better than the other (though one is obviously better for the marketing dept.)
Just don't assume that "built for speed" always means "built to be fast" -- a confusing but important distinction. :-)

Speculate...

[skinlayers]

What I really want to know is how much this chip is going to cost. If its cheap for Apple to put 2 or 4 of these in a machine, then how much will it matter that an expensive P4 (P5) out performs it? Hmmm.... The current Wind-Tunnel G4s raised a few eyebrows when it first came out do to the new case design. These things were designed to disapate heat! A HUGE (7 lbs) heat sink w/ matching fan, a small case fan, 2 fans on the power supply, and a ton of ventalation in the back. WAY more cooling that those 2 little G4s require. I think Apple is trying to avoid the fiasco it had with the Sawtooth (1st gen) G4s where they just slapped a G4 onto a G3 mobo. This time around, I believe they're releasing a new mobo first and then put a new proc in it down the road. I've also read stuff in forums suggesting that the power supply for the Wind-Tunnel had way more juice than the system currently demands. Can anyone out there do the math on this? We know how much power the PPC 970 eats. Can we figure out how much heat the Wind-Tunnel case is designed to disapate? What about how much power the power supply is putting? With these numbers, can we figure out how many PPC 970 the Wind-Tunnel case could power and cool? I've been suffering with a 266MHz G3 iMac, and I refuse to upgrade until Apple comes out with a system that really is worth that premium they charge, and a G4 is not it.

Re:They should make it work three ways

[.pentai.]

Why would they want to?
Intel and AMD have the x86 market pretty well locked down.

More importantly, why would ANYBODY want to implement the x86 ISA (Instruction Set Architecture or smtn like that). It's the most horrid instruction set in use today.

Some instruction sets can't really be mapped to others easily, and optimizing for good performance with PPC would probably not have good x86 performance anyways.

In Pentiums and Athlons, the instruction set isn't really emulated. It's translated to a smaller instruction set (uops, iops, pick whatever term you like and run with it). However, these smaller sets are still made pretty much specifically to cover the overlying ISA (x86 in this case).

Re:They should make it work three ways

[stripes]

More importantly, why would ANYBODY want to implement the x86 ISA (Instruction Set Architecture or smtn like that). It's the most horrid instruction set in use today.

Because that is where most of the desktop CPU money is going, some of the high end, and frighteningly enough a fair bit of embedded CPU money too.

In short if you can navigate the patent mine field, the brutal competition mine field, and deal with the instruction set making things a royal bitch doing an x86 CPU is a total no-brainer.

In Pentiums and Athlons, the instruction set isn't really emulated. It's translated to a smaller instruction set (uops, iops, pick whatever term you like and run with it). However, these smaller sets are still made pretty much specifically to cover the overlying ISA (x86 in this case).

Other then needing a whole new decoding front end, and being forced to use a trace cache because decoding multiple instructions in x86 land is very hard... the instruction thing isn't a big deal. Handling the odd-ball 80 bit FP format is. So is emulating all of the trap stuff and the other little odd bits close to the instructions set (like the MMU).

A big pain. But with much of the effort not being where folks think it is!

Re:They should make it work three ways

[Lars T.]

You mean like AMD? With more than 20% marketshare and bleeding money? Yeah, right, I know this is just because of their Flash memory business.

Re:They should make it work three ways

[Paul Neubauer]

One of the early planned PPC chips had that idea in mind, by pretty much adding an x86 processor and logic to figure out what instruction set it was getting and where to send it. The idea was that then there would be no barrier to using PPC code - it could run x86 code to replace existing systems and run PPC as well. Thus it would be a transitioning thing.

The x86 world seemed to move faster than the design for this and it fell away. It made more sense to concentrate on PPC stuff rather than try to do PPC and changing x86 stuff. Also, if it ran x86, why should anyone bother to write for PPC?

The difference is Pentiums and Athlons are intended to be x86 family upgrades, while the PPC is not. The PPC 970 is meant as an upgrade to earlier PPCs. One could as well ask why AMD doesn't make an Athlon that can run PPC code.

Re:They should make it work three ways

[puto]

Because they would have to license the x86 architecture from the respective owners. AMD and INTEL have licensing agreements.

Puto

Re:unfotunatly Apple is going with Intel instead..

[I_am_Rambi]

A few things wrong with this document.

• This information is from a Giga Information Group perspective. - This is what they think.
• There has been no "official" annoucement from Apple.
• Its highly unlikely that Apple will go with two different chips. Story Here [slashdot.org].

I think Apple will stick with a company that it knows, IBM, since they have been working together for years. It doesn't seem that Apple will just jump ship to the x86 platform. This would also mean redoing the Mac OS X code and optimization (not like they will have to do some anyway, but they will have to do more). It is highly unlike that Apple will go with a heat producing, energy wasting x86 Intel chip.

They wouldn't have to redo anything...

[Chibi Merrow]

As was mentioned in this previous article [slashdot.org], Mac has been maintaining a seperate port of MacOS X for x86 in synch with the PPC version... I still remember some promotional material pre-OS X talking about an x86 version of Mac OS X being released that lacked the functionality to run Mac OS Classic apps (I think it was called Blue Box?).
Are they going to jump ship to x86? Not likely if they can help it... but they're keeping the option open. Kind of like how Dr. Evil KNOWS his plans will never fail, but he always has that Big Boy rocket hidden in the back--just in case. ;)

And who ya calling energy wasting? My Palomino keeps my room nice and toasty on those lonely nights and makes great julienne fries! ;)

Re:They wouldn't have to redo anything...

[Zelet]

I know that keeping your room warm was a joke... but I have an Athlon XP 2000 system that, when running, I have to close the heater vent so that my room doesn't get too hot.

Re:They wouldn't have to redo anything...

[Chibi Merrow]

Actually not that much of a joke... when I moved into my new house I noticed that the area under my desk stays noticably warmer than the rest of the room and my feet were kept downright toasty if I propped them up on top of my Athlon XP 1800 tower... I think the GeForce 4 and the 400w power supply with all the fans piping heat outta the back add to the effect also. :)

Apple selects a winner!

[doorbot.com]

It is highly unlike[ly] that Apple will go with a heat producing, energy wasting x86 Intel chip.

...because PPC chips completely disobey the laws of physics, producing neither heat, nor "waste energy" (perhaps through the production of heat?). Yes, it is PPC, miracle of modern technology, standing up for the common man against the perils of Thermodynamics!

Re:unfotunatly Apple is going with Intel instead..

[WatertonMan]

Apple will almost certainly go with 970 and not switch to Intel for the following reasons: 1. It is difficult to emulate PowerPC with Intel (although the reverse isn't *that* difficult). Apple would need a PowerPC emulator so that all that software (including OSX software) isn't lost. 2. Apple wants to differentiate itself somewhat from the PC. 3. IBM appears to be moving up after the several years of problems with Motorola. The downside is that by the time a 970 board is out it will definitely be in the middle of the pack relative to the PC world. That means that Apple still will have computers that are more expensive than the PC world and that aren't as fast. Of course I think OSX is sufficiently better than either Linux or WinXP for a workstation that I'll stick with it. But Apple best hope that IBM gets large yields on time and perhaps with better speeds than expected.

Re:unfotunatly Apple is going with Intel instead..

[dolanh]

My guess is that we're gonna see "Four brains are better than one" right around the time the 970 arrives, and that this time it will make the Mac competetive (unlike the Daystar days).

Re:unfotunatly Apple is going with Intel instead..

[dolanh]

Nobody ever said premium Mac systems were cheap. Quad proc Daystars were quite expensive in the day.

I said "competitive", but I meant in performance terms. Price competitiveness is a whole different issue, though as another poster hinted, price/performance might not be as bad as one would think, esp. if IBM isn't plagued by the same fab issues Motorola has come across with the G4 (and history has shown that they probably won't be).

Re:unfotunatly Apple is going with Intel instead..

[cehardin]

Ok, apple most likely isn't going to go with Intel CPUs, but one of your reasons is wrong.
Mac OS X binaries are capable of being FAT. They can contain both PPC and Intel instructions. OS X binaries are actually folders which can contain multiple architecture implementations within them. This also applies to the "libraries". Ok, the Framework bundles.

Re:unfotunatly Apple is going with Intel instead..

[Lars T.]

Yes, the binaries can be "FAT" - but currently not a single one is. IOW all software would have to be recompiled (if that is possible at all).

Re:unfotunatly Apple is going with Intel instead..

[Toraz Chryx]

"There's nothing magical or mysterious about emulating one 32-bit architecture on another, and writing a PowerPC emulator for the x86 would not be significantly different to writing an x86 emulator for the PowerPC"

Go count up the PPC registers.. then the registers in the x86 architecture...

With JIT "acceptable" speed would be possible, but I wouldn't expect more than 601-66 performance from a high clocked P4 running interpretive PPC emulation..

Re:unfotunatly Apple is going with Intel instead..

[DrinkDr.Pepper]

finally they'll see that clock speed does make a difference Clock speed is something Intel uses to bolster their performance claims and give people an excuse to upgrade to the newest model. Clock speed tells very little about the performance of a computer. Look at AMD's athlon. Many reviews like the ones on tom's hardware [tomshardware.com] show that running Windows on a "slower" athlon yeilds better performance than a comparably clocked P4. If you meant that finally, if apple runs on x86, there will be a better benchmark between Windows and MacOS, you would be more accurate. Until that happens you are comparing two different fruits.

Re:unfotunatly Apple is going with Intel instead..

[Joey7F]

One time someone asked me "Will this faster processor help me download quicker or what"

I stared at him and just said "Yes...yes it will"

--Joey

Re:unfotunatly Apple is going with Intel instead..

[DrinkDr.Pepper]

Sure, clock speed makes a difference, but only on the same chip. The post I was commenting on implied that you could compare the clock speed of an Intel machine to the clock speed of an Apple machine. For such a comparison clock speed is wholly irrelevant.
P.S. My 333Mhz P2 runs great at 400Mhz, but largely because Intel underclocked the identical core to run at 333Mhz. Intel plays up the importance of clock speed, so they do dumb things like underclocking, and multiplyer locking.

Re:I am tired of 64 bit lies ! (40 bit only, folks

[KewlPC]

*Sigh* The size of a CPU's address/data bus does not reflect a processor's "bitness". 64-bit means that it has a 64-bit word size (as opposed to the 32-bit word size on x86 processors), 64-bit registers, etc. Most 64-bit CPUs don't actually have a 64-bit address bus. Like you said, the Alpha's is 48-bit. This is usually done to keep the pin count down to a sane level (if you need all the physical RAM that a 64-bit address bus would provide, you need something bigger than a desktop CPU). You can expect that as 64-bit chips become more common on the desktop to see somebody introduce a 64-bit CPU that has a 64-bit address bus just so that they can say, "Hey, look, we have a 64-bit address bus, the other guys only have a 48-bit one!" and (like you are trying to do) will insinuate that this means the competition's CPUs aren't "true" 64-bit (even though they are).

I dunno 'bout Macs (I don't know the M68k's "bitness"), but Intel introduced the 386 (their first 32-bit CPU) in 1986. And I certainly don't think the M68k was a RISC processor.

at current prices and projected prices, 512 gigabytes or RAM will barely cost more than a couple of the fastest processors of this type.

Really? I would LOVE to be able to buy 512 gigabytes of RAM for the cost of a couple of fast desktop processors. Don't forget that the PowerPC 970 is meant to be a desktop processor.

Blah blah blah...

[KewlPC]

I specifically said, "I dunno 'bout Macs..." because I wasn't trying to make a "See? Intel is better than Mac" post. I was just giving the date at which Intel introduced their first 32-bit processor.

And now that you mention it, I do remember reading that the M68k was 32-bit, but it only had a 24-bit address bus, which meant the max. amount of RAM it could physically have was 16 megabytes. Again, I'm not trying to bash anybody, I'm trying to point out that your "64-bit CPUs aren't really 64-bit because they only have a 48-bit address bus" argument is flawed.

Why you went off on the whole Apple vs. Wintel thing is beyond me, but if you want to play ball, OK. For the record, the PC wasn't meant to compete with the Lisa or the Mac, and both of those computers were introduced after the PC. The original IBM PC was a competitor to the Apple II, but more oriented towards business use rather than home use. If you remember, the Apple II also used a cassette tape drive (just like the original PC), but, like the PC's successors, the PC-XT and the PC-AT (all modern PCs are descended from the PC-AT), later had the ability to use floppy drives and hard drives.

The 1982 lisa had windows, scolling, dialogs, fonts, buttons, WYSIWYG text editing with graphics, etc.

Which were all "borrowed" from Xerox PARC. The fact that Apple later whined and bitched about Microsoft "borrowing" those ideas from the Lisa and/or Mac (when Apple themselves had stolen those concepts from somebody else in the first place) is too amusing for words. I can't stomach Bill Gates, but I have just as hard of a time putting up with Steve Jobs ("You stole Windows! It's not fair! We stole it first!").

And as for Mac OS always being 8 years ahead of Windows, well, I'm no lover of Windows, but Windows had preemptive multitasking years before Mac OS (Windows got it in Win95, Mac OS didn't have it until OS X).

the Apple II had 75% of us market

Although I don't have any hard facts, I have a hard time with this. It wasn't like IBM and Apple were the only players in the personal computer market. There was Commodore with their highly successful Commodore 64 computer (not to mention the Commodore PET, VIC-20, and Commodore 128), Sinclair, the TRS-80 (from Tandy and RadioShack IIRC), and a whole host of others.

Re:Blah blah blah...

[Maxwell]

And as for Mac OS always being 8 years ahead of Windows, well, I'm no lover of Windows, but Windows had preemptive multitasking years before Mac OS (Windows got it in Win95, Mac OS didn't have it until OS X).

Windows NT/2000XP had real pre-emptive multitasking before the half bit crappy win95 implementation. 1993? Think NT 3.1 and Nt 3.51. Those OS's, much maligned then are now the foundation for MS future OS's...

Re:Blah blah blah...

[KewlPC]

I'm not saying they copied the look & feel of the GUI developed at Xerox PARC, just that they copied the concepts and ideas from them.

Re:All this talk...

[Roadmaster]

" OpenMP is a specification for a set of compiler directives, library routines, and environment variables that can be used to specify shared memory parallelism in Fortran and C/C++ programs." All that would have to be added to gcc are the "compiler directives", as the "library routines" and "environment variables" aren't directly a part of the compiler.

Now, openMP is good for programming extremely high-performance shared-memory applications, like scientific computation applications and stuff like that. It really sounds like overkill for a desktop environment where it's probably easier to program a multithreaded application with standard IPC mechanisms where communication is required. And really high-performance applications could also be programmed using MPI and a message passing communication scheme, which is far more widely used (compare the # of people who know about openmp versus those who know about mpi), probably wouldn't be much less efficient, and would quite likely scale much better than a shared memory implementation.

Re:All this talk...

[gnuadam]

0. When I say I want openMP added to gcc, that sort of implies that I want the compiler directives added, and the library routines added to the standard libraries that are shipped with the compiler. I realize gcc isn't going to affect any environment variables.

1. I write scientific code. That's how I know openmp. I think it's great for that.

2. It's not really overkill, because it's quite easy to program for (in a portable way!) Much easier than fork(), and IMHO easier than pthreads.

3. Admittedly, I've never needed much in the way of IPC for the codes I've written for smp (scientific codes on smp machines don't need much of it) but you could probably use a pipe, a socket, or whatever else. I do mostly want it for the scientific uses, though.

4. MPI is good. But openMP is like 1000x easier to write for, and on good hardware is usually better ... for my problems.

5. If IBM, or apple even, makes affordable, good smp boxes with this processor, openmp would be quite useful.

6. The same features it's good at in science ought to make it perfect for other processor intensive tasks. Anything that needs a for (do) loop can be scaled quite well. Anything that has chunks that don't need communication can be scaled well as well. I imagine video/sound encoding might be easily parallelized using this...much easier than pthreads, and for this mpi would be overkill, don't you think?

7. All I'm saying is that openMP is out there, is supported on most commercial compilers, and it's noticably missing from gcc. *I* would use it. I suspect many more people would use it if it was available .... especially if 4 processor boxes become available on the commodity market as people seem to be expecting (dreaming) in this topic.