A History of PowerPC 193
A reader writes: "There's a article about chipmaking at IBM up at DeveloperWorks. While IBM-centric, it talks a lot about the PowerPC, but really dwells on the common ancestory of IBM 801" Interesting article, especially for people interested in chips and chip design.
IBM also says Screw you to intel (Score:4, Informative)
Big Endian (Score:5, Funny)
Re:Big Endian (Score:5, Informative)
X86 is little endian, which is chunked-up and backwards.
Example:
View the stored number 0x12345678.
Big endian: 12 34 56 78
Little endian: 78 56 34 12
Clear as mud?
Re:Big Endian (Score:3, Interesting)
Then again I could be completely wrong.
Re:Big Endian (Score:4, Informative)
Re:Big Endian (Score:2)
I thought every modern CPU (ia32 excluded either way) was bi-endian cabable but I guess I was wrong.
Re:Big Endian (Score:5, Informative)
Little-endian has some nice hardware properties, because it isn't necessary to change the address due to the size of the operand.
Big Endian:
uint32 src = 0x00001234;
uint32 dst1 = src;
uint16 dst2 = src;
Little Endian:
uint32 src = 0x00001234;
uint32 dst1 = src;
uint16 dst2 = src;
The processor doesn't have to modify register values and funk around with shifting the data bus to perform different read and write sizes with a little-endian design. Expanding the data to 64 bits has no effect on existing code, whereas the big-endian case will have to change all the pointer values.
To me, this seems less "chunked up" than big endian storage, where you have to jump back and forth to pick out pieces.
In any event, it seems unnecessary to use prejudicial language like "normal" and "chunked up". It's just another way of writing digits in an integer. Any competent programmer should be able to deal with both representations with equal facility.
Being unable to deal with little-endian representation is like being unable to read hexadecimal and insisting all numbers be in base-10 only. (Dotted-decimal IP numbers, anyone?)
Big-endian has one big practical advantage other than casual programmer convenience. Many major network protocols (TCP/IP, Ethernet) define the network byte order as big-endian.
Don't ignore integer sizes! (Score:5, Insightful)
So, you're reading in an array of integers, which are now 64 bit vs 32 bit and no code change is needed?
Programs NEED to know the size of the data they're working with. Simply pulling data from an address without caring for it's size is a recipee for disaster!
Re:Big Endian (Score:5, Informative)
One more big advantage of the big-endian byte order is that 64-bit big-endian CPUs can do string comparisons 8 bytes at a time. This is a big advantage where the length of the strings is known (Java strings, Pascal strings, burrows-wheeler transform for data compression) and still an advantage for null-terminated strings.
I'm not aware of any such performance advantages for the little-endian byte order.
The main advantage of little-endian byte order is ease of modifying code written in assembly or raw opcodes if you later decide to change your design and go with larger or smaller data fields. The main uses for assembly programming are very low-level kernel programming (generally the most stable part of the kernel code base) and performace enhancement of small snippets of code that have been well tested and profiled and are unlikely to change a lot.
I agree that an decent programmer should be able to deal with either endianess, but the advantages of the little-endian byte order seem to be becoming less and less relevant.
Re:Big Endian (Score:2)
Both Endians (Score:2, Informative)
The PPC ISA has support for both big- and little-endian modes. However, the little-endian mode is a bit screwy. There are some appnotes on the Motorola website on using little-endian mode.
Re:IBM also says Screw you to intel (Score:4, Interesting)
Does this mean that ALL next-generation consoles (next Gamebuce, PS3 and Xbox2) will use a IBM chip?
Re:IBM also says Screw you to intel (Score:4, Informative)
Theres a pantload of info here [ibm.com].
Re:IBM also says Screw you to intel (Score:2, Interesting)
It has been known for some time that the PS3 would based on the IBM "Cell" project, which is some sort of Power derivative (a.k.a. PPC). So yes, as far as anyone knows, the next generation consoles will all be powered by the PPC. With Generation 5 (G5) and beyond, it looks like the PowerPC Revolution [amazon.com] may finally be closer to reality. :-)
"Chips May Physically Reconfigure Themselves" (Score:2)
The Sony connection is nothing surprising, as it has already been announced that Sony is creating silicon with IBM for their next-gen chipset. I wouldn't be the slightest bit surprised to see a PS3 running on a cluster of rebranded (and possibly modified) PPC chips.
P.S. Does anyone know why Windows has never been adapted to run under PPC? While the transition for Apple from PPC to x86 may be without technical merit, why h
Re:"Chips May Physically Reconfigure Themselves" (Score:5, Informative)
Errm, actually, it WAS. See for instance
http://home1.gte.net/res008nh/nt/ppc/default.htm [gte.net]
Re:"Chips May Physically Reconfigure Themselves" (Score:3, Informative)
Re:"Chips May Physically Reconfigure Themselves" (Score:3, Informative)
Re:IBM also says Screw you to intel (Score:3, Informative)
Re:IBM also says Screw you to intel (Score:2)
Actually IBM claims that their version of SMT is much superior to HT with 30-60% improvement over the improvements gained bt Intel with HT. Specifically they say the expect to see 35-40%+ improvements using SMT under heavy usage.
If those numbers are right then it would be significantly better than HT. Although in fairness to Intel they are comparing Power5 server chips with PC-roots Xeon processors so there's probably alot more headro
Re:IBM also says Screw you to intel (Score:2)
Re:IBM also says Screw you to intel (Score:3, Informative)
Re:IBM also says Screw you to intel (Score:2, Informative)
This is really cool stuff. IBM is a little late to the game in some regards, SGI has been doing this stuff for years in IRIX on their MIPS machines. But hey better late than never...
Re:IBM also says Screw you to intel (Score:5, Informative)
Well sort of (Score:4, Informative)
Example: Windows is running on slice 1, BSD on slice 2, and Linux on slice 3.
BSD gets a kernel panic and crashes, the slice is restarted without affecting the remaining running OS's. It's, for the lack of a better term, Hyperthreading for the whole computer.
Re:Well sort of (Score:2)
MVS... (Score:2, Informative)
Damn them! Dam them to HELL!!!!
Chip design in a nutshell for the lazy: (Score:3, Funny)
Fry in oil or bake in oven.
Salt.
Enjoy!
Re:Chip design in a nutshell for the lazy: (Score:2, Funny)
Re:Chip design in a nutshell for the lazy: (Score:3, Funny)
Re:Chip design in a nutshell for the lazy: (Score:2)
*sigh* (Score:3, Insightful)
Re:*sigh* (Score:2)
LK
Re:*sigh* (Score:4, Interesting)
Supposed to deliver? OpenBSD people thought that as well, and got the OS running on it. Now OpenBSD consider Pegasos a scam operation and has pulled the support for Pegasos from CVS :
R.I.P. OpenBSD/Pegasos - All the story [deadly.org]
Re:*sigh* (Score:2)
Re:*sigh* (Score:3, Interesting)
Woudn't it be great to be a able to pick up and ASUS or Epox PowerPC motherboard and run it with a Power970FX?
One can dream.
Guide to the PowerPC architecture (Score:5, Informative)
Re:Guide to the PowerPC architecture (Score:2)
To be honest, I'm not sure how much of a benefit it provided, but I used it anyway.
LK
Re:Guide to the PowerPC architecture (Score:2, Informative)
You'd go into its folder and see "Peak (604)" or "Deck II (604)" to let you know that it was going to use your particular processor to its best performance.
Nice 42 year backward compatibility (Score:5, Insightful)
John.
Re:Nice 42 year backward compatibility (Score:2)
Modern mainframes still take punch cards too!
I code for mainframes and I can tell you most of the source code has comments from the 70's and early 80's, it's pretty neat to see that stuff.
Re:Nice 42 year backward compatibility (Score:2)
You know there's probably just one of each locked way down in the basement working on this, afraid of the sunlight.
Re:Nice 42 year backward compatibility (Score:2)
Interesting quote from the article (Score:5, Funny)
You find Douglas Adams fans all over, don't you?
Re:Interesting quote from the article (Score:2)
Obligatory Quote of the Day (Score:5, Funny)
I didn't think it was possible to use the words "Fishkill" and "hip" in the same sentence with a straight face.
Power PC was the death of the MIPS processor (Score:4, Insightful)
Gone where the intelligent disk and network subsystems. No more die cast aluminimum chassis.
Whilst I can understand in some sectors the incessant drive for highest MIPS per $, is there not also a place for bullet proof proven technology?
Re:MIPS (Score:2)
Yeah, I remember (Score:4, Interesting)
Re:Yeah, I remember (Score:2)
Re:Yeah, I remember (Score:5, Informative)
What Intel did was include RISC architecture in around the x86 instruction set to create the pentium pro, pentium II, III, etc. Otherwise they would have been killed.
Infact IBM was correct. Cisc was dying. THe pentium1 could not compete agaisnt the powerpc unless it had a very high clock speed. All chips today are either pure risc or a hybrid cisc/risc like todays Althons/Pentium's. The exception is the nasty Itanium which is not doing too well
Re:Yeah, I remember (Score:3, Insightful)
Nice PowerPC Roadmap (Score:5, Informative)
PowerPC in PlayStation 2? Huh? (Score:2)
Correct me if I'm wrong, but isn't the PlayStation 2's EmotionEngine processor a proprietary MIPS-derived ISA?
Re:PowerPC in PlayStation 2? Huh? (Score:4, Informative)
link [uiuc.edu]
So yes, it is in a way MIPS derived, but the MIPS core does very little of the actual processing, it's more of a bootloader and I/O coprocessor.
So what HDL do they use? (Score:3, Interesting)
Re:So what HDL do they use? (Score:4, Informative)
Too scary! (Score:2)
Re:Too scary! (Score:2, Informative)
Mostly IBM-developed schematic capture, simulation, and physical design tools. I also did some work on test structure verification using an IBM-designed tool.
Tools available [ibm.com] in the current ASIC methodology are on the IBM website. Some of these would have been used back then, too.
One of the coolest things about PowerPC chips (Score:5, Funny)
Say what? (Score:2)
Computer history IS IBM-centric (Score:5, Insightful)
Re:Computer history IS IBM-centric (Score:3, Informative)
It was Lyons Tea Shop Company, of all unlikely contenders, who married "electronic programmible devices" to IT.
Of course when they realised thier mistake they went hell for leather to redress the balance. But...amazingly.....they were totally off the ball **again** with microcomputer technology.
Re:Computer history IS IBM-centric (Score:2)
When the PC came out they looked at it more as a smart terminal to an IBM mainframe. Not a serious contender for any "real" work.
For those who want PPC970 without getting a Mac... (Score:2)
Sure its pricey, but I suppose if your interested in such price isn't the key issue.
Sunny Dubey
Re:For those who want PPC970 without getting a Mac (Score:5, Funny)
LK
Re:For those who want PPC970 without getting a Mac (Score:5, Informative)
RS/6000 [ibm.com]
Or, a Power-based IBM workstation,
Workstation [ibm.com]
Re:For those who want PPC970 without getting a Mac (Score:2, Funny)
About My Resume... (Score:2)
Not sure I'd want that on my resume. Wasn't IBM's greatest success -- even given their unmatched maketing department.
Re:About My Resume... (Score:2)
I think you can say a lot of stuff about IBM, but "unmatched marketing department" ? *ahem*
How goes the old joke ? "How do the US solve their drug problem ?" "They legalize drugs and leave marketing to IBM."
Most print campaigns of the last years IBM had over here in Germany sucked mightily at least IMO. There were some really funny few, those were great, but most of them were either hard to understand or just boring.
Re:About My Resume... (Score:2)
The two comments that stick with me from the earlier days of IBM are:
1. The guy who gets the rights to put the IBM logo on an office trashcan will make a fortune selling them.
2. Nobody ever got fired for buying IBM.
Re:About My Resume... (Score:3, Informative)
Re:About My Resume... (Score:2)
About 1/2 of modern architectural concepts that we take for granted in current mircroarchitectures were first introduced in stretch. It was that important.
Re:About My Resume... (Score:2)
Could it be because they sold about one of them, and that was to the government who buys all kinds of stuff they don't really get their money's worth out of afterwards? (The San Diego Supercomputer Center is another example of having bought a dud or two of research projects that have never worked as promised.)
You may ar
200 instructions at once? (Score:5, Insightful)
(Which is great until you mispredict a branch, of course. :-)
Re:200 instructions at once? (Score:5, Informative)
Although, it should be noted that the pipeline depth for the POWER4 is just 15 stages (as opposed to the P4 which has, IIRC, 28 stages), so while a branch misprediction is quite bad, it's not as bad as some architectures. My understanding is that, in order to achieve that 200 IPC number, the POWER4 is just a very wide superscalar architecture, so it simply reorders and executes a lot of instructions at once. Plus, that number may in fact be 200 micro-ops per second, as opposed to real "instructions" (although, that's just speculation on my part... it's been quite a while since I read up on the POWER4), as the POWER4 has what they term a "cracking" stage, similar to most Intel processors, where the opcodes are broken down into smaller micro-ops for execution.
Quotable! (Score:2, Offtopic)
Large and hyphenated! It's nice when technical writers get to slip a little something in on the side.
Article may need a bit of work (Score:2)
Also, when you say that POWER4/PPC970 can process 200 instructions at once, you need to explain a bit better what having "instructions in flight" really means. It's not that it can do 200 instructions every clock cycle.
Submitted this on the feedback form at the bottom of the article as well. The above just don't ring right as expressed.
Sounds fishy to me... (Score:5, Interesting)
Maybe this is a sign that it has been too long since I learned about computer architecture, but is it really fair to call a CPU that has a deep pipeline, a crypto-RISC CPU?
When my buddy first told me about this exciting new RISC idea one of the design goals was each instruction was to take a single instruction cycle to execute. Isn't this completely contrary to a deep pipeline? The Pentium 4 has a 20-stage pipeline IIRC.
Was I wrong to laugh when I heard hardware manufacturers claim, "sure, we make a CISC, but it has RISC-like elements .
What I am reminded of is the change in how musicians are classified. When I grew up rock music was just about all that young people listened to. Rap and punk music had never been heard of. And country music was considered incredibly uncool. Now country music's coolness factor has grown considerably. And a strange thing has happened. Lots of artists who were unquestionably considered in the Rock camp back then, like Neil Young, or Credence Clearwater, are now classified as Country music, as if they had never been anything else.
It has been a long time, but I remember learning in my computer architecture course about wide microcode instruction words, and narrow microcode instruction words. Wide microcode instruction words allowed the CPU to do more operations in parallel. Ie. the opposite of a RISC. So, I ask in perfect ignorance -- how wide are the Pentium 4 and Athlon microcode?
If I am not mistaken the Transmeta was a very wide instruction word. And if I am not mistaken, doesn't that make it the opposite of a RISC?
Re:Sounds fishy to me... (Score:3, Informative)
Also, things like Out-of-order-execution and Branch-prediction makes more sense for a RISC instruction set (so I was told
But I more or less agree with you that a long pipeline is somewhat contradictory to the idea of RISC.
Re:Sounds fishy to me... (Score:3, Informative)
Not really, the idea is to make every instruction simple.
Reduced Instruction Set Computer
The side effects of this are that every instruction can be the same length thus simplifying the complex decoding process of a CPU.
x86 can be multiple bytes in length, whi
Re:Sounds fishy to me... (Score:2)
Re:Sounds fishy to me... (Score:5, Informative)
No, in fact pipelining is central to the entire concept of RISC.
In traditional CISC there was no pipelining and operations could take anywhere from 2-n cycles to complete -- at the very least you would have to fetch the instruction (1 cycle) and decode the instruction (1 cycle; no, you can't decode it at the same time you fetch it -- you must wait 1 cycle for the address lines to settle, otherwise you cannot be sure of what you're actually reading). If it's a NOOP, there's no operation, but otherwise it takes 1+ cycles to actually execute -- not all operators ran in the same amount of time. If it needs data then you'd need to decode the address (1 cycle) and fetch (1 cycle -- if you're lucky). Given that some operators took multiple operands you can rinse and repeat the decode/fetch several times. Oh, and don't forget about the decode/store for the result. So, add all that up and you could expect an average instruction to run in no less than 7-9 cycles (fetch, decode, fetch, decode, execute, decode, store). And that's all presuming that you have a memory architecture that can actually produce instructions or data in a single clock cycle.
In RISC you pipeline all of that stuff and reduce the complexity of the instructions so that (optimally) you are executing 1 instruction/cycle as long as the pipelines are full. You have separate modules doing the decodes, fetches, stores, etc. (and in deep-pipeline architectures, like the P4, these steps are broken up even more). This lets you pump the hell out of the clockrate since there's less for each stage of the pipeline to actually do.
Modern CPUs have multiple everything -- multiple decoders, fetchers, execution units, etc. so it's actually possible to execute >1 cycle/cycle. Of course, the danger to the pipelining is that if you branch (like when a loop runs out or an if-then-else case) then all those instructions you've been decoding go out the window and you have to start all over from wherever the program is now executing (this is called a pipeline stall and is very costly; once you consider the memory delays it can cost hundreds of cycles). Branch prediction is used to try and mitigate this risk -- generally by executing both branches at the same time and only keeping the one that turns out to be valid.
Was I wrong to laugh when I heard hardware manufacturers claim, "sure, we make a CISC, but it has RISC-like elements
Yes, because neither one exists anymore. CISC absorbed useful bits from RISC (like cache and pipelining) and RISC realized there was more to life than ADD/MUL/SHIFT/ROTATE (oversimplification of course). The PowerPC is allegedly a RISC chip, but go check on how many operators it actually has. And note that not all of them execute in one cycle. x86 is allegedly CISC, but, well... read on.
how wide are the Pentium 4 and Athlon microcode?
The x86 ISA has varying width. It's one of the many black marks against it. Of course, in reality, the word "microcode" isn't really applicable to most CPUs nowadays -- at least not for commonly used instructions. And to further muddy the picture both AMD and Intel don't actually execute x86 ISA. Instead there's a translation layer that converts x86 into a much more RISC-y internal ISA that's conducive to running at more than a few megahertz. AFAIK, the internal language is highly guarded by both companies.
If I am not mistaken the Transmeta was a very wide instruction word. And if I am not mistaken, doesn't that make it the opposite of a RISC?
Transmeta and Intel's Itanium use VLIW (very large instruction word) computing, which is supposed to make the hardware capable of executing multiple dependant or independant operations in one cycle. It does so by putting the onus on the compiler
Re:Sounds fishy to me... (Score:2)
Early RISC (for example early SPARC) didn't even have integer multiply!
VLIW seems to have some life in high-throughput DSP. Texas Instruments makes some 8-instructions-at-once DSPs.
VLIW is very impressive. (Score:2, Informative)
I like this quote (Score:5, Insightful)
Can anyone tell me where I can buy a G5 laptop?
G5 laptop? (Score:3, Funny)
Sure! Send me your CC info and I promise I'll send you a G5 laptop! I'm also selling Playstation 5s [penny-arcade.com].
Re:I like this quote (Score:2)
Of course, I don't know *when*, but you never asked *when*.
Next Apple Mac? (Score:2)
http://www.macosrumors.com/33004M.html
Please note that MOSR has a long history of being completely and utterly wrong in their predictions, so don't get your hopes too high...
On a similar note... (Score:2, Interesting)
This is revolutionary: Self-evolving machines. (Score:2, Interesting)
Did you read this? [businesswire.com] Look at the second-to-last paragraph:
That is the first step in self-evolving machines.
Yes, it is a minor step, but it is a friggin first step, OK? If they can pull this off, the
The complete history (Score:2, Interesting)
Best article ever! (Score:2)
Seriously, check these quotes from the IBM site: [blockquote] Thus, in the days when computing was still so primitive that people thought that digital watches were a neat idea, it was CMOS chips that powered them. [/blockquote] [blockquote]Figure 1. It's wafer-thin[/blockquote] [blockquote]One of the reasons for that is IBM's new top-of-the-line fab in Fishkill, New York. The Fishkill fab is so up-to-date that it is capable of producing chips with all of the latest acronyms, from copper CMOS XS to Silicon
Something wrong? (Score:2)
POWER3
Released in 1998: 15 million transistors per chip
The first 64-bit symmetric multiprocessor (SMP)
Didn't several companies have 64-bit multiprocessor machines out back then? Unless I'm mistaken, Sun's Starfire was before then, having up to 64 UltraSparc II's - which, as I recall, were 64-bit chips. And that's just Sun, ignoring the other players.
So, it is just that they used "SMP", as opposed to other forms of multiprocessing, or is my memor
Impressive (Score:3, Informative)
That's quite impressive. Throw the 970 in that mix and it's even more impressive. The bottom line is that Intel isn't alone at the top of the mountain when it comes to producing high quality, fast, and reliable chips. On a side note, as a soon-to-be-graduating CS major, I dream about working at a place like IBM.
Re:Motorola (Score:4, Informative)
They gave up on desktop PPC. They still do a lot of new PPCs, just working on improving MIPS/watt instead of pure MIPS. Embedded space is a lot higher volume and bigger profit than Apple.
Re:Motorola (Score:4, Interesting)
1) 80% of all G4s sold have gone to Apple. So targetting the larger embedded market is a marketing excuse, a failure, or both.
2)Motorola's fabrication facilities have been in horrendous shape for at least 4 years. High failure rates, In one location, they even quit running the fans to "save energy."
3)Motorola has failed to advance in the embedded world as well. TiVO and many others are switching from PPC to MIPS because Motorola's stuff is not moving forward.
4)Brain-drain and 'Dilbert syndrome' have plagued Motorola's CPU division since Apple killed the clones in 1997. They are spinning off that part of their business, but there's no indication that the situation has improved.
Re:Motorola (Score:2)
2) No knowledge, but wouldn't surprise me.
3) They do okay in my application segment (automotive embedded). Not great, but okay.
4) I don't work there, so no knowledge.
None of this changes my point: Motorola still produces and actively develops PPC.
Re:Motorola (Score:3, Informative)
So, you could say Motorola is giving up on semiconductors... but the division that worked on the G4 will continue to work on PPC. Just under a different name.
Re:Motorola (Score:2, Interesting)
Yes, Motorola did build and promote thier hardware, but OS manufacturers did not even seem to be able to get decent device drivers working for it, let alon do an efficient port. In the end it was a box that could (almost)