Comment Re:Integrated graphics in the CPU? (Score 1) 254
this is totally architecture dependent.
Intel needed their large caches for netburst because pipeline stalls where extremely costly, and the memory had a very large latency, they solved both issues in core 2, with very advanced prefetchers to hide the latency, and a shorter pipeline to make stalls less costly.
AMD on the other hand, moved the memory controller on die with the advent of the Athlon64, which made for extremely low memory latency. Back in the day i read up on cache sizes for AMD chips (because i was going to buy a chip, and wanted to know if going for the large l2 was worth it). As it turns out, in not a single benchmark did a chip with 1 mb l2 beat a chip with only 128k l2 (an 1/8th) at the same clock by more then 10% (and the 10% was an extreme).
The only reason todays chips have such large amounts of L3 is because we dont just have one core sucking down data, we have four (or six, or in case of nehalem, 4+4 virtuals). If intel still had the old FSB, i3/5/7 would need even bigger caches