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Intel

New Intel 8-way Chipset 84

VJ writes "Intel just announced their new 8 way SMP chipset for use with PentiumIII-Xeons. A summary of features: 3X100 buses (2 for CPU's, and 1 for I/O. (The chipset appears to function to some degree as a crossbar switch, between the three buses) Cache coherencey features allow better utilization of L2 cache, other stuff too..) We'll have to wait and see, but this might be a relatively cheap way to get raw CPU for enterprise environments.. (Relative to Sun or HP or SGI)"
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New Intel 8-way Chipset

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  • WHat's wrong with using 64 bit pointers? And why would you have to recompile? Isn't it possible for the kernel to recognize both kinds and translate them accordingly?

    I do agree that the segment stuff is a big and horrible hack rather then a real solution.
  • They could use OS/2 Warp Server.
    It is available NOW and can handle up to 64-CPU and claims to be optimized for 8-CPU.
    The scaling is terrific. Just a bit below 1:1 linear beyond 2 and 4 CPU.
  • Actually, you are right on the money. The EV6 architecture uses a 100MHz clock, but sends data on both the rise and fall if the line signal.

    What this really accomplishes is the ability to send twice the amount of information of a "standard" 100MHz BUS. The 200MHz name is technically wrong with regards to clock signal, but right with regards to data transfer speed.

    Bottom line is that regardless of what it's called, it's still faster than my PIII-450 bus and I want one :)




    Never underestimate the power of stupidity in large groups
  • Unless they've changed recently, Intel's always seemed to use Unixware for their past SPEC runs. I see no reason they'ed switch to Linux for this (given the 8 processors of the system).
  • this may be good for vmware. Imagine being able to tell vmware that each OS has 2 processors, and then running win NT and Solaris on top of Linux. 2 procesors for sun 2 for NT and the rest for Linux :-). Ahh to be able to surf the web, use the webcam, and have other OS'es working for you in the background :-) oh the power if nothing else just to have that kind of computing power at home. :-) drool
  • Well, two avis, but you're got a point. Perhaps some info about the two movies. They are 29 fps with sound and Indeo5 encoding. Be's Indeo decoder is most likely straight c or c++, so of course it's a bit slower than it could be.

    The previous reply is right too. Unused cpus are wasted cash.. but then, that's what rc5 is for right? :)
  • by phej ( 21792 )
    > So AMD is actually running the bus below spec so to say even

    You would too... transmission lines are hard to deal with. AMD is smart enough to understand that:

    If you build it, they will come. (But only if it's cheap)

    The engineers at digital understand this (sorta), but their principal target is not the $2000 machine.

  • ... recently released not too long ago.

    The Athlon is an impressive chip. Let us wait till the end of October to decide which company (Intel, AMD) has the bigger balls and better staying power!

    By then, AMD will have their Server and Enterprise Editions (smells like Win2K) and their motherboards with SMP and all that mess.

    Keep also in mind that the baddest motherboard makers (Tyan, ABit, AOpen, etc.) will be releasing motherboards for the Athlon.

    If Tyan made a board for the Athlon that is similiar to their Thunderbolt [tyan.com] for Intel... [official drool]


    ChozSun [e-mail] [mailto]
  • No it can't support celeron (its slot2)... and it shouldn't. Anyone who needs 8-way proccessing (1)can afford the damn xeons and (2)would never stand for celerons. The point of the xeon is (1)big-ass cache and (2)error correcting/reliability. A celeron system (esp. overclocked) is nowhere near as reliable as a xeon and never will be (it's just not meant to serve). No, having the 8-way set be for xeon only is wise.
  • OS/2 scales very well to 8 CPU's - way better than NT or Linux do. For years, OS/2 has been able to scale well to 16 CPU's.
  • This stuff has been in the pipe for a long long
    time. It appears that large corporate customers have been testing it since February - and they did not test it as
    a file and print server. We are talking serious stuff here, no funny small web server, but SAP R/3 and the like. The stuff you run a large company on.

    Do you really believe a Company like Compaq would
    come up with an Intel box with TPC-C numbers as high as these as an answer to some AMD pre-release info?
    Getting these numbers means squeezing these boxes
    to the limit, and that takes weeks, and a lot of
    nightshifts... would be a rather large effort. Believe me, this is a serious architecture, and not at all comparable to the PentiumPro 8way
    (not scaling at all) that used to be around a year ago.

    And yes, you are absolutely right on the bandwidth
    issue, but keep in mind: The core of this technology is not the single bus, it is the high-speed crossbar switch (Profusion) that sits in the middle of the architecture. read the specs: It actually has ten unidirectional ports that appear as five bi-directional ports. With the 100-MHz buses attached, there is a peak throughput on each port of 800 MB/s. With all five ports, the crossbar switch allows a maximum peak throughput of 4.0 GB/s. Ok, that's theoretical - as is the EV6 stuff.
  • All the "top tier" server vendors are rushing like mad to get 8-way Xeon systems out the door. They're most likely not going to want to support a second CPU/Chipset combination. If the Athlon was pin compatible with the Xeon, that'd be a different story, no matter what the performance advantages of EV6.

    What AMD needs to do is first ship the chip, in volume and avoid all the glitches that've plagued it in the past. Then they can try to make some deals with the server vendors. Until then, SMP Athlons are really going to be the domain of workstation-users and hobbyists.
  • Call me crazy, but won't this actually be slower? I mean, putting that many chips on the same bus ... even if you do sync in the manner they're talking about, that doesn't help much when you're working with large volumes of data


    This is correct. Intel seems to have made a half-hearted switch to a crossbar bus system, with the result that their bus can still be easily saturated. Programs that aren't memory-intensive will still benefit from the SMP. Programs that are memory-intensive will saturate the bus and leave many of the processors idle.


    It'll be good for Quake III, but I suspect anyone in the know will probably stick with a RISC design.


    Memory performance has nothing to do with whether the processor is RISC or CISC. Memory bus design is the only thing that matters here. Point-to-point implemented on a crossbar bus beats a shared bus no matter what chips are used.


    Getting back to the Holy War, most modern implementations of CISC are almost as efficient as RISC (look at the guts of the K7 design for an example). You wind up with an extra stage in your pipeline for decoding, and that's about it. RISC is generally favoured because there's no real reason to use CISC any more (higher code density isn't as vital), and removing CISC support simplifies chip design and optimization.


    The main problem with Intel chips is that they've been repeatedly extending a design that wasn't designed to be extensible, in a rather kludgy manner. They're still stuck with it, because if they switch to a completely new architecture they lose their installed base of customers. This is why the Merced still supports x86 modes.

  • by nion ( 19898 )
    been there, done that, installed RH 5.2 on it, got nearly 4k bogomips.

    the joys of working with pre-release product.
  • I want more info though...
  • how long before linux can run (well) on such an architecture?
  • Any idea how Linux will use this much main memory?

    A large ram disk for databases?
    A larger virtual address space?

    or better yet, a _huge_ addition for my "Little Computer People" house. =^]
  • oh yeah, it detected and ran all EIGHT processors fine, i didn't really do much with it other than rc5 to see if it would hold up under the load (it did) and kicked out about 9.5-10Mkeys with 550Mhz processors.

    i used what was the latest kernel at the time...2.2.5 or 7...it's been soo long. ;)
  • by Anonymous Coward
    if you can't keep it fed. A single PIII can saturate a 100MHz bus, putting 4 of them on a single bus is going to kill performance of any sort of memory-bound applications. The big boys usually know what they are doing, HP, Decpaq/Alpha and SGI all know how to keep their processors fed.
  • by tamyrlin ( 51 )
    The EV6 bus used by Ahtlon and Alpha CPU:s is probably much better for SMP than Intel's bus.
    To begin with, the EV6 bus is clocked at 200 MHz whereas the Intel bus is clocked at 100 MHz.

    The EV6 bus is also a point to point architecture, not really a bus in fact. The drawback is that the motherboard is more difficult to design.

  • I was unable to find any mention of what OS was used for these benchmarks. Realistically, only SCO or Linux seems probable (since the application in question is Oracle8), and I do not know whether more recent in-house tuning has allowed Linux to scale past 4 CPUs on x86 machines. But as of a few months ago, NT and Linux both went from near-linear scaling to a near-plateau beyond 4 CPUs, so I am wondering if they didn't use SCO.

    Regardless, it's odd that they don't say.

  • Here are a couple of screenshots:



    http://www.isk.kth.se/~eb99jolu/
  • Well, it's on their list (first, 'coz the different OSes are in alphabetical order, and no vendor name was given for Linux), presumably Intel itself is fairly confident that it'll not make them look like utter fools. It's going to be hard for them to justify Linux remaining on that list unless it demonstrably does better than, with, say, just 4 processors.
  • People are *still* talking about bogomips as if they had any value as a benchmark whatsoever?

    I thought we cleared this up around 1995 or so ... guess not ...
  • databases
    big fat ones
    dont need a ramdisk, just let the database eat it all up.
  • There isn't really a way to reprogram the cpu to act like a new cpu. Other than the chipset, socket layout, power supply and software issues, the instruction decoder only understands the instruction set for one chip type, the microcode can be done differently depending on how the chip works, eg: AMD v Intel, but it can't make the x86 instruction set look like the sparc instruction set. Even if you turned off all of the non-essential instructions it still wouldn't be RISC, it would be CISC with a lot of wasted space. RISC is designed from the ground up with smaller arithemtic/logic units to run at higher clock rates. It also uses the higher speeds of internal cache to avoid "slower" ram intensive operations.

    The intel assembly language is horrible to program in. I've had an easier time writing assembly code for a Vax than trying to get anything to run on x86. Its basicaly the 10th generation of new stuff slapped onto old stuff with backwards compatability. The segment registers are all worthless with a 32 bit adressing register. The lack of a large number of register such as on an r6000 or ultraSparc make the chip very memory intensive, it can't page registers after a context switch. So intel just spends most of its time waiting for the memory bus to get back with the data instead of doing actual calculation.

    The best way to squeeze out more calculations per clock cycle are by overclocking or redesigning the chip, trying to one-up Intel's microcode, assuming you could even get access to it and had the ability to reprogram it, would most likely just make it run slower because you don't understand the system as well as they do.

  • I was under the impression that EV6 was only a 100MHz clock, but using the UDMA trick (of utilizing both the rising and falling edges of the signals to send data) to double the data bandwidth. Does anyone know what this is called, and what the most accurate way to discuss speeds of this kind of deal are?
  • I would like to add that Celerons can't do 8 way and 4 way for that matter .. the most you'll get out of that PII core is dual..
    Same goes for "real" PII and PIII chips, they can do dual at most..
    Xeons and PPo's can 4 way and up..

    But I'm not sure if going "intel" is such a good idea if you need that many cpus, SGI, Sun, and Digital/Compaq seem much further along in that area..
  • There aren't any so far as I know. Are there quad athlons available? How about dual? What about an Athlon single CPU machine? They don't exist.

    They will, sure, but corporates trust Intel, just as they trust Microsoft and they used to trust IBM. It's going to take more than just a flash in the pan to jump over to Athlon servers... Show successive generations widening the performance gap vs. Intel, and IT departments will bite. Until then, you'll probably see them drop them by power-user desktops asking them to check them out and let them know if there's anything funky about them.

    I know I'm going way off topic here, but bringing AMD into this does them a great disservice, being that they're not equipped at this point to take on this market segment.
  • What part of raw CPU is it that implies need for >32GB memory? Or >4GB, for that matter?
    There are plenty of tasks that require lots of CPU but will do quite fine on a 32 bit platform. Like, say, compiling kernels. ;)
  • So where are people supposed to get eight-way (or four-way or two-way) Athlong motherboards and systems? The Profusion is out now, Athlon SMP is expected to debut on the market next year, from what I've seen.
  • What good is a massive power server if the protocols for sharing/managing it aren't there?
  • Why pay $100,000 US for an 8 way Intel system when one can get a Sun Box with the possibility of more CPU's, a proper bus, and just as many applications. When I say applications, I mean the kind (High end db, video. .. )that people with this kind of money and need use.

    my 2cents :)
  • that is, 50% improved performance on an online transaction processing benchmark [tpc.org] when growing the number of processors by 100%:

    Compaq ProLiant 8000-550-2M (Pentium III Xeon 4 CPU 550 MHz 2 MB cache NT4SP4 /MSSQL7.0) 26,560.40
    Compaq ProLiant 8000-550-2M (Pentium III Xeon 8 CPU 550 MHz 2 MB cache NT4SP4 /MSSQL7.0) 40,013.30

    Of course with TPC-C, systems are obscenely expensive since they configure them with so much disk that the system won't be I/O bound. But this looks likely to be an NT marketing bullet. Prepare your responses now!

    --LinuxParanoid
    (Hey, just because we're paranoid of Microsoft doesn't mean they're not out to get us...)
  • Any idea how Linux will use this much main memory?

    A large ram disk for databases?
    A larger virtual address space?


    It *won't* be a larger virtual address space. How would we do that? Use 64 bit pointers on a 32 bit architecture, and force everyone to recompile? Or use the God-awful segment/offset crap that Intel seems to have a fetish for, and still force everyone to recompile?

    Technically it would be possible to give 4GB... but it would be a hideous hack - NT will do it; Linus (and therefore Linux) won't.

    There's a patch in that will give databases access to "anonymous pages" of memory - I'm not sure how they get accessed, but apparantly it's in a fashion both Linus and the large DB makers are happy with.

    But damn it, I tried to program Win16 once, and I thank God Linus doesn't want to get bogged down in a segmented architecture more than necessary. If you want more than 32 bits of addressable memory, don't use a 32 bit machine, damn it!
  • Sorry about the last post; forgot to escape the less than and greater than signs...

    Any idea how Linux will use this much main memory?

    A large ram disk for databases?
    A larger virtual address space?


    It *won't* be a larger virtual address space. How would we do that? Use 64 bit pointers on a 32 bit architecture, and force everyone to recompile? Or use the God-awful segment/offset crap that Intel seems to have a fetish for, and still force everyone to recompile?

    Technically it would be possible to give less than 4GB to each process, simply allowing multiple processes access to different 4GB chunks so that the total RAM used is more than 4GB... but it would be a hideous hack - NT will do it; Linus (and therefore Linux) won't.

    There's a patch in that will give databases access to "anonymous pages" of memory - I'm not sure how they get accessed, but apparantly it's in a fashion both Linus and the large DB makers are happy with.

    But damn it, I tried to program Win16 once, and I thank God Linus doesn't want to get bogged down in a segmented architecture more than necessary. If you want more than 32 bits of addressable memory, don't use a 32 bit machine, damn it!
  • So when will we be able to order 8-way systems with this chipset from our favorite Linux hardware vendors?

    Penguin has been offering 8-way systems for a while using another chipset solution, but the price for those systems is over $100,000, while 4-way systems are more like $12,000, last I checked.
  • You can boot off the serveRAID thing. We did. Contact bdragoo@thomasaquinas.edu for more information about booting off the Netfinity's serveRAID.
  • I could cluster my home PCs to run Beowulf. But that doesn't matter because I've nothing to run on it.

    Have you?

    Beowulf is neat, but I've yet to see a killer app for the home user or hobbyist. (Those were never the targets, but...)

    Just wondering because everyone seems to regard Beowulf as the greatest thing since armpit hair, and I'm sure not everyone has an app for it.
  • I don't think Quake3 will have much benifit at all over 2 processors, and none over 3..
    John Carmack set up two processes, one for the rendering pipeline, one for the physics and other enviornment code. If you have another thread doing your openGL thing, then maybe 3 would help.. The rest would basically sit around and heat your room...
    NOw that I think of it, I should get one of these as a RC5 cracker and spaceheater ;-)
  • Just wondering because everyone seems to regard Beowulf as the greatest thing since armpit hair, and I'm sure not everyone has an app for it.

    If armpit hair was a great thing.. or a bad thing.. or something to compare Beowulf clusters to. (and no, I'm not being one of those people that you're speaking of that regards "Beowulf as the greatest thing since..."). I'm just saying that, hmm, body hair and hard ware.. interesting mix.
  • OK, so run MOSIX [jhu.edu] so processes will the automatically scattered across the cluster.
  • I guess those pentium-133 Compaqs at work suck at serving too.
  • When I was assembling 7000 M10's a little while ago, there was a special program where for a few bucks you could upgrade your machine to 8 way when the new board came out.

    My problem with Linux under the Netfinity was that ther serverRAID adapter would not work (I believe that they have release a driver now, but it's not bootable)

    I'm kinda curious how 8 processors fit into the new assembly - Are the voltage regulators gone?
  • beos sure is great. with an 8 CPU configuration, playing an AVI will send 5 of the CPU's to over 50% usage :P
  • What the hell?

    Hey, I know AMD doesn't have a lilly white past, but this is ridiculous. If any company wants decent SMP performance at a 'relatively' cheap price ( again, compared to the -=real=- heavy chips ) then Athlon is the only choice. Any corporation that would choose Intel over the Athlon High End series either has a special deal with Intel, or an uninformed IT department.


  • wouldn't you have to store that kind of system in a meatlocker to keep it from burning up?

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