The reason is because the Icelandic alphabet has two different letters that produce a sound that could be written "th" in English. The letter eth (Ð or ð) is a voiced "th", like in "they" or "this"; whereas the letter thorn (Wikipedia link, since Slashdot won't render it) is unvoiced, like in "thistle" or "theater". By convention, eth is transliterated as "d", whereas thorn is transliterated as "th". It does make some sense, as "d" is a voiced consonant, so that in addition to the look being similar, the naive pronunciation isn't horribly wrong. (And it means that someone seeing a "th" in an English transliteration of Icelandic text knows that it's unvoiced, so they'll get the pronunciation right.) And for better or for worse, it's the accepted transliteration, so if you want to fight it you're fighting against convention.

The gross transliteration error that kills me is when someone substitutes P or p for the thorn and turns something like Thingvellir into Pingvellir. That's just horribly wrong.

Exactly correct. If the target date for an "interim test storage site" is 2021, that's only 7 years out.

Let's allow a year to figure out what the specs ought to be, a year to request and evaluate proposals from possible contractors, a year to build prototypes, a year of testing, a year to fix problems identified in testing, a year to manufacture the first few final-version railcars, and a year for overruns. That's a seven-year timetable right there.

Unless we want to be running late, paying tons of money out in overtime, and getting railcars that kind-of-sort-of work right most of the time...then yeah, right now is a good time to start on this stuff.

I don't know about rural Japan, but I found the OSM data far better when I visited Tokyo a few months ago. Google didn't know building names and placed a load of things that we were trying to visit a few blocks away from where they actually were. This was very frustrating as the web site that we were using to find vegetarian restaurants used Google maps - we spent half an hour one lunchtime walking in the wrong direction, because we'd come to a junction and, according to the Google map needed to turn left and would then see our destination on the right. It turned out, when we eventually found it, that we should have turned right.

I use OSMAnd on my phone[1], but my girlfriend recently bought a Windows Phone and I've been very impressed with Nokia's mapping app (I actually like a lot of what Microsoft's done with Windows Phone 8, but it's a strange mix of very polished and well-designed UI parts and completely unfinished parts with missing features). It's good to see more competition with Google maps, which is becoming increasingly entrenched in spite of the fact that the UI is pretty poor in many regards and the mapping data is terrible. For example, here they're missing (or have in the wrong places) most of the cycle paths, which ends up with people regularly getting lost if they rely on Google, in spite of the fact that all of this data is in OpenStreetMap.

[1] For me, it's the killer app for Android. Offline maps, offline routing, and open source backed by high-quality mapping data from OpenStreetMap. I use the version from the F-Droid store, which doesn't have the limitations of the free version from Google Play and it's one of the few open source apps that I've donated money to.

Remember when the SoundBlaster Live! came out and Creative Labs were telling you that it had as much processing power as a Pentium 166MHz MMX, dedicated entirely to sound processing? Well, it turns out that now you can have far more CPU power than that dedicated entirely to sound processing without custom hardware...

They're a pain for people on both sides of the ISA.

The compiler has to find an instruction that can run after the branch. This is normally trivial for calls, but for conditional branches within a function it's often difficult to find an instruction that you can put there. It has to be one that is either from before the jump (or in both basic blocks after the jump), but that the branch doesn't depend on (because it's executed after the branch instruction). This means that you quite often end up padding the delay slots with nops, which bloats your instruction cache usage. On a superscalar implementation this is the only cost, but on a simple in-order pipeline it's also a completely wasted cycle.

On the other side, it's a pain to implement. It made sense for a three-stage pipeline in the original MIPS, because you always knew the next instruction to fetch. A modern simple pipeline is 5-7 stages though, so your branch is still in register fetch (if there) by the time the delay slot is needed. It doesn't buy anything and it means that, if you're doing any kind of speculative execution (even simple branch prediction, which you really need to do to get moderately good performance) then you have an extra dependency to track - you can't just use the branch as the marker and flush everything after it, you need to do some reordering. In a superscalar implementation, you need to do even more complex things in register renaming to make it work.

I have a cooler master haf-x. It breathes out the top. Works great, and I can put it right up against a wall, because the intlet fan is on the other side, unless I am an idiot and put the fan side against the wall. Even then there are two other fans, one in front and one in back to try to limit the damage if I am an idiot.
I can't speak enough praise about this case. From the access points, to cable grommets, to incredible airflow, to built in sdata and usb frontside.
I priced an alienware to a homebuilt with this case, and went homebuilt. I'll never look back. Alienware was probably 50-75% more and with them you don't get to pick the top of the line brand new components, if that is your choosing.
This is not a slashvertisement, as I don't have any ad links for you to click, just my opinion and I hope you are able to use it to some benefit.

Regular PCs don't heat up because regular PCs don't produce a great deal of heat. Enthusiast PCs do, but Enthusiast PC owners know better, and if they don't then they are the perfect target market for a replacement PC.

No idea. I don't know if the instructions for computing PC-relative addresses in an ISA without an architectural PC are patentable. They also exist in RISC V (not sure which came first), so if they do then it's going to be a problem for Kriste et al. Nothing else in there is especially novel: like ARMv8, it's a nicely designed compilation target, but it doesn't do anything that's especially exciting.

I didn't look at the floating point stuff in much detail, so there may be something there, although the biggest changes in recent versions of the MIPS specs have been that they're more closely aligned with the IEEE floating point standards, so it's hard to imagine anything there.

The biggest difference between MIPS64r6 and ARMv8 is that the MIPS spec explicitly reserves some of the opcode space for vendor-specific extensions (we use this space, although our core predates the current spec - it's largely codifying existing opcode use). This allows, for example, Cavium to add custom instructions that are useful for network switches but not very useful for other things. ARMv8, in contrast, expects that any non-standard extensions are in the form of accelerator cores with a completely different ISA. This means that any code compiled for one ARMv8 core should run on any ARMv8 implementation, which is a big advantage. With MIPS, anything compiled for the core ISA should run everywhere, but people using custom variants (e.g. Cisco and Juniper, who use the Cavium parts in some of their products) will ship code that won't run on another vendors' chips.

Historically, this has been a problem for the MIPS ecosystem because each MIPS vendor has forked GCC and GNU binutils, hacked it up to support their extensions, but done so in a way that makes it impossible to merge the code upstream (because they've broken every other MIPS chip in the process) and left their customers with an ageing toolchain to deal with. I've been working with the Imagination guys to try to make sure that the code in LLVM is arranged in such a way that it's relatively easy to add vendor-specific extensions without breaking everything else.

Imagination doesn't currently have any 64-bit cores to license, but I expect that they will quite soon...

Assuming that your code doesn't do anything that is vaguely MIPS specific. If it is, then there is little benefit in using MIPS32r2 now - ARMv7 is likely to be closer than MIPS32r2 to MIPS32r6 in terms of compatibility with C (or higher-level language) source code compatibility.

Basically, because the MIPS ISA sucks as a compiler target. Delay slots are annoying and provide little benefit with modern microarchitectures. The only way to do PC-relative addressing is an ugly hack in the ABI, requiring that every call uses jalr with $t9 in the call, which means that you can't use bal for short calls. The lwl / lwr instructions for unaligned loads are just horrible and introduce nasty pipeline dependencies. The branch likely instructions are almost always misused, but as they're the only way of doing a branch without a delay slot there's often no alternative.

There's no price yet because they're giving away the first production run to people who are going to do interesting things with them. Unfortunately, this is a really bad time to do anything MIPS related (and I say this as someone who hacks on a MIPS IV compatible softcore and the LLVM MIPS back end). Imagination has just released the MIPS64r6 and MIPS32r6 specs. These are the biggest revisions to the MIPS ISA since MIPS III, which introduced 64-bit support. They've removed a load of legacy crap like the lwr and lwl instructions and the branch-likely instruction family and added things like compact (no delay slot) branch instructions, the requirement that hardware supports unaligned loads and stores (or, at least, that the OS traps and emulates them), and added much better support for PC-relative addressing. The result is a nice ISA, which is not backwards compatible with MIPS32r2 or MIPS64r2, the ISA that these boards use. Any investment in software for MIPS now is going to be wasted when products with the new ISA come out.

For building big C++ projects, as long as the disk (yay SSDs!) can keep up, you can throw as many cores as you can get at the compile step and get a speedup, then sit dependent on single-thread performance for the linking. I got a huge speedup going from a Core 2 Duo to a Sandy Bridge quad i7, then another noticeable speedup going to a Haswell i7 in my laptop. The laptop is now sufficiently fast that I do a lot more locally - previously I'd mostly work on a remote server with 32 cores, 256GB of RAM (and a 3TB mirrored ZFS array with a 512GB SSD for ZIL and L2ARC), but now the laptop is only about a factor of 2 slower in terms of build times, so for developing individual components (e.g. LLVM+Clang) I'll use the laptop and only build the complete system on the server.

There are several nice features of a landline, but they can't (in the UK, at least) compete on price. The line rental alone for a landline costs more than I spend on calls on my mobile (pre-pay, no contract, no monthly fees). Calls from my mobile are 3p/minute, a landline is £16/month. I'd need to spend almost 9 hours on the phone each month before I spent as much on my mobile as a landline would cost me before I even made any calls. And then, for the kicker, the calls from the landline cost 9p/min (+15p setup) for calls to other landlines or 12p/min (+15p setup) for calls to mobiles. There's no possible justification for calls from the landline costing 3-4 times as much as calls from the mobile on top of the extortionate line rental. If I wanted to pay BT even more, for another £3 I could get free evening and weekend calls to landlines, but calls to mobiles would still be the same price. For £7.50 on top of the line rental, I'd get free calls to landlines, and calls to mobiles would only be twice the cost of my mobile. Almost everyone I call has a mobile though, so in exchange for paying BT an amount equivalent to about 12 hours of calls on my mobile per month, I could then pay double per minute what I pay for calls on my mobile with no line rental.

I enjoyed that article, but it's worth noting that vi actually is standard.

Ok, have to give SOME credit to SC5 for this. You don't have to micromanage getting utilities to everyone. The distribution system appears random and thus can be sucky if your building is out of water or power and is off on a long branch with a bunch of buildings in between. It will take forever to get the utility watering or powering them again.
Upgradable buildings is another plus, though I have hosed myself several times by not leaving space to upgrade around the building itself. Come on people, build UP!
Most of the rest of SC5 is suck, suck and more suck.

Wish I could get myself to stop playing it.