No idea. I don't know if the instructions for computing PC-relative addresses in an ISA without an architectural PC are patentable. They also exist in RISC V (not sure which came first), so if they do then it's going to be a problem for Kriste et al. Nothing else in there is especially novel: like ARMv8, it's a nicely designed compilation target, but it doesn't do anything that's especially exciting.

I didn't look at the floating point stuff in much detail, so there may be something there, although the biggest changes in recent versions of the MIPS specs have been that they're more closely aligned with the IEEE floating point standards, so it's hard to imagine anything there.

The biggest difference between MIPS64r6 and ARMv8 is that the MIPS spec explicitly reserves some of the opcode space for vendor-specific extensions (we use this space, although our core predates the current spec - it's largely codifying existing opcode use). This allows, for example, Cavium to add custom instructions that are useful for network switches but not very useful for other things. ARMv8, in contrast, expects that any non-standard extensions are in the form of accelerator cores with a completely different ISA. This means that any code compiled for one ARMv8 core should run on any ARMv8 implementation, which is a big advantage. With MIPS, anything compiled for the core ISA should run everywhere, but people using custom variants (e.g. Cisco and Juniper, who use the Cavium parts in some of their products) will ship code that won't run on another vendors' chips.

Historically, this has been a problem for the MIPS ecosystem because each MIPS vendor has forked GCC and GNU binutils, hacked it up to support their extensions, but done so in a way that makes it impossible to merge the code upstream (because they've broken every other MIPS chip in the process) and left their customers with an ageing toolchain to deal with. I've been working with the Imagination guys to try to make sure that the code in LLVM is arranged in such a way that it's relatively easy to add vendor-specific extensions without breaking everything else.

Imagination doesn't currently have any 64-bit cores to license, but I expect that they will quite soon...

Assuming that your code doesn't do anything that is vaguely MIPS specific. If it is, then there is little benefit in using MIPS32r2 now - ARMv7 is likely to be closer than MIPS32r2 to MIPS32r6 in terms of compatibility with C (or higher-level language) source code compatibility.

Basically, because the MIPS ISA sucks as a compiler target. Delay slots are annoying and provide little benefit with modern microarchitectures. The only way to do PC-relative addressing is an ugly hack in the ABI, requiring that every call uses jalr with $t9 in the call, which means that you can't use bal for short calls. The lwl / lwr instructions for unaligned loads are just horrible and introduce nasty pipeline dependencies. The branch likely instructions are almost always misused, but as they're the only way of doing a branch without a delay slot there's often no alternative.

There's no price yet because they're giving away the first production run to people who are going to do interesting things with them. Unfortunately, this is a really bad time to do anything MIPS related (and I say this as someone who hacks on a MIPS IV compatible softcore and the LLVM MIPS back end). Imagination has just released the MIPS64r6 and MIPS32r6 specs. These are the biggest revisions to the MIPS ISA since MIPS III, which introduced 64-bit support. They've removed a load of legacy crap like the lwr and lwl instructions and the branch-likely instruction family and added things like compact (no delay slot) branch instructions, the requirement that hardware supports unaligned loads and stores (or, at least, that the OS traps and emulates them), and added much better support for PC-relative addressing. The result is a nice ISA, which is not backwards compatible with MIPS32r2 or MIPS64r2, the ISA that these boards use. Any investment in software for MIPS now is going to be wasted when products with the new ISA come out.

For building big C++ projects, as long as the disk (yay SSDs!) can keep up, you can throw as many cores as you can get at the compile step and get a speedup, then sit dependent on single-thread performance for the linking. I got a huge speedup going from a Core 2 Duo to a Sandy Bridge quad i7, then another noticeable speedup going to a Haswell i7 in my laptop. The laptop is now sufficiently fast that I do a lot more locally - previously I'd mostly work on a remote server with 32 cores, 256GB of RAM (and a 3TB mirrored ZFS array with a 512GB SSD for ZIL and L2ARC), but now the laptop is only about a factor of 2 slower in terms of build times, so for developing individual components (e.g. LLVM+Clang) I'll use the laptop and only build the complete system on the server.

There are several nice features of a landline, but they can't (in the UK, at least) compete on price. The line rental alone for a landline costs more than I spend on calls on my mobile (pre-pay, no contract, no monthly fees). Calls from my mobile are 3p/minute, a landline is £16/month. I'd need to spend almost 9 hours on the phone each month before I spent as much on my mobile as a landline would cost me before I even made any calls. And then, for the kicker, the calls from the landline cost 9p/min (+15p setup) for calls to other landlines or 12p/min (+15p setup) for calls to mobiles. There's no possible justification for calls from the landline costing 3-4 times as much as calls from the mobile on top of the extortionate line rental. If I wanted to pay BT even more, for another £3 I could get free evening and weekend calls to landlines, but calls to mobiles would still be the same price. For £7.50 on top of the line rental, I'd get free calls to landlines, and calls to mobiles would only be twice the cost of my mobile. Almost everyone I call has a mobile though, so in exchange for paying BT an amount equivalent to about 12 hours of calls on my mobile per month, I could then pay double per minute what I pay for calls on my mobile with no line rental.

I enjoyed that article, but it's worth noting that vi actually is standard.

I'm certainly going to get some really nice subwoofer to go with this.

With 16 GPRs, it has fewer registers than all the major RISC architectures other than 32-bit ARM, just as the 32-GPR System/3x0 (including its 64-bit z/Architecture version) does. It's less register-limited than x86, but that's not setting the bar very high. (Note that IBM recently added instructions to z/Architecture that do arithmetic on the upper 32 bits of the GPRs; that suggests that there's some register pressure with only 16 GPRs, although if they still have to make use of base registers, even with PC-relative branches, that might add some additional pressure that x86-64 doesn't have.)

No, they didn't; x86-64 has, as noted, only 16.

Limited their what?

Also, Olympus E-1 pro digital camera (just 5 megapixels, but weather sealed and with 160,000 shutter actuations and counting).

Oh, and printing stuff.

There's "the alternatives" and there's "the alternatives worth considering". The latter category excludes the developing countries in question, as well as the US. Hopefully the people in charge of health care in Canadian governments (federal and provincial) are looking at the alternatives in the latter category to see what they can learn from them.

Perhaps you're referring to some news of which I'm not aware.

That isn't answering the question I asked.

The question I asked was "You can't trade off, say, transistors used for registers (especially given that the bigger processors do register renaming, so you have more hardware registers than the actual RISC/CISC instruction set provides) for transistors used for some other purpose?"

I said nothing about keeping all the same functionality, if by "functionality" you mean, for example, "on-chip caches of the same size" and "same number of hardware registers including ones used for renaming of the architected registers" or "complexity of the branch prediction hardware" or .... Yes, there may be tradeoffs you have to make in how you use your transistors, but if the benefits of the additional registers outweigh whatever performance benefits you lose by reducing the size of other functional units by however much the additional registers require, that might be the right tradeoff to make.

Ok, thanks for checking. You seem to be correct, apparently the buyer simply wasn't paying attention.