That is one disappointing summary. Marketing cut-and-paste mixed with a bunch of irrelevancies.
This is RISC-V. That crucial fact and what it means is completely omitted from the summary. RISC-V is an open ISA (Instruction Set Architecture) out of Berkeley. By open I mean you can go over here and get the stuff you need to make a real CPU without any license costs or other IP entanglements. Open and free from the silicon up. RISC-V is a new 32/64/128 bit ISA with a clean, comprehensive design that is free of legacy cruft, bad ideas and other flaws, and the core instruction set has recently been permanently frozen so it's no longer a moving target for developers.
SiFive is a fabless semiconductor company "founded by the creators" of RISC-V to produce real silicon. HiFive is a little demo board with a (rather fast) RISC-V SOC. Some people have gotten hung up on the FTDI thing; that's just a UART to provide USB; it doesn't mean this is some kind of proprietary trap. Because the ISA is fully open competitors are free to make their own RISC-V designs as well and embed/attach whatever UARTs they want. Competitors are also free to use Eagle, gEDA, damp napkins are whatever they wish to design boards for their RISC-V chips, so that Altium hang up in summary isn't particularly relevant either.
Google has been a sponsor of RISC-V work and has been hosting conferences for the platform. They are also actively developing Go on RISC-V and there have been some rumors about Google using RISC-V to displace proprietary CPUs in their operations.