It depends on if they emulate it by translation and shadowing, or by interpretation. Software translation is rather fast, but not native-fast. To get native-fast, you have to go native.
I've been suggesting an accelerator chip (maybe even off-die) that decodes x86 instructions into the internal RISC instructions stored in the ICache, but people keep telling me it's impossible because... they're stupid. Modern x86, x86-64, and ARM chips all read instructions in their ISA and translate to an internal CPU RISC ISA, to the point that x86-64 chips actually translate x86 instructions to take advantage of around 60 hardware registers thanks to having not just twice as many GPRs (16!), but those GPRs being 64-bits wide (32 GPRs), plus the EBP, ESP, and EIC registers being 64 bits wide and only validly addressing a 32-bit address space (3 more registers). Multiple instructions hitting the same memory won't just work on cache (fast), but will actually load that cache line to register (extremely fast) and operate a series of instructions there--even out-of-order instructions.
No doubt the instruction decoder would be large-ish, and access to its own (I4) cache would prove a performance boon if that cache is kept consistent with actual RAM. Nevertheless, it should be roughly-trivial to produce a CPU chipset that can execute both x86-64 and ARM64 code, in the same way it's roughly-trivial to produce a CPU chipset that executes both x86 and x86-64 or ARM and THUMB. These aren't simple tasks by any means; but the fact is we routinely create chipsets which execute an ISA, and chipsets which execute multiple ISAs, and even chipsets which execute old ISAs while automatically leveraging internal facilities such as registers available to new ISAs (which isn't impressive when you think about OOE, parallel execution, and branch prediction). x86-64 is related to x86, but only at face value; they're different instruction sets, just like ARM and MIPS are different, and it should be fairly easy--not cheap, mind you--to wedge x86-64 in with ARM.