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Average Ratings 0 Ratings

Total
ease
features
design
support

No User Reviews. Be the first to provide a review:

Write a Review

Description

Oasys-RTL meets the demand for enhanced capacity, quicker runtimes, elevated quality of results (QoR), and physical awareness by performing optimization at a more abstract level while also incorporating integrated floorplanning and placement features. This tool significantly improves the quality of results by facilitating physical accuracy, efficient floorplanning, and rapid optimization cycles, ensuring timely design closure. Its power-aware synthesis capabilities encompass support for multi-threshold libraries, automatic clock gating, and a UPF-based multi-voltage domain flow. During the synthesis process, Oasys-RTL intelligently inserts the necessary level shifters, isolation cells, and retention registers according to the power intent specified in the UPF framework. Additionally, Oasys-RTL can generate a floorplan directly from the design's RTL by applying dataflow and adhering to timing, power, area, and congestion constraints. It adeptly incorporates regions, fences, blockages, and other physical directives via advanced floorplan editing tools while automatically positioning macros, pins, and pads to optimize the layout. This holistic approach ensures that designers can efficiently manage complex designs and meet stringent performance requirements.

Description

The Solido variation-aware design solutions, alongside IP validation, library characterization, and simulation technologies driven by cutting-edge AI, are utilized by thousands of designers at leading semiconductor firms across the globe. This integrated suite features AI-enhanced SPICE, Fast SPICE, and mixed-signal simulators that empower clients to significantly expedite crucial design and verification processes for advanced analog, mixed-signal, and custom IC designs. It delivers the industry's quickest and most thorough integrated IP validation solution, ensuring complete and seamless IP quality assurance from the design phase all the way to tape-out, encompassing all design perspectives and IP updates. Moreover, this comprehensive AI-driven design environment facilitates both nominal and variation-aware verification of custom IC circuits, achieving full design coverage with far fewer simulations while maintaining the accuracy comparable to brute-force methods. Furthermore, it offers rapid and precise library characterization tools that leverage machine learning for enhanced performance and reliability.

API Access

Has API

API Access

Has API

Screenshots View All

Screenshots View All

Integrations

No details available.

Integrations

No details available.

Pricing Details

No price information available.
Free Trial
Free Version

Pricing Details

No price information available.
Free Trial
Free Version

Deployment

Web-Based
On-Premises
iPhone App
iPad App
Android App
Windows
Mac
Linux
Chromebook

Deployment

Web-Based
On-Premises
iPhone App
iPad App
Android App
Windows
Mac
Linux
Chromebook

Customer Support

Business Hours
Live Rep (24/7)
Online Support

Customer Support

Business Hours
Live Rep (24/7)
Online Support

Types of Training

Training Docs
Webinars
Live Training (Online)
In Person

Types of Training

Training Docs
Webinars
Live Training (Online)
In Person

Vendor Details

Company Name

Siemens

Founded

1847

Country

United States

Website

eda.sw.siemens.com/en-US/ic/oasys-rtl/

Vendor Details

Company Name

Siemens

Founded

1847

Country

United States

Website

eda.sw.siemens.com/en-US/ic/solido/

Product Features

Product Features

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