Siemens Aprisa Description
Creating designs at advanced process nodes necessitates a novel approach to place-and-route to handle the growing intricacies involved. Aprisa stands out as a detail-route-focused physical design platform tailored for contemporary SoCs. Operating as a complete RTL2GDSII solution, Aprisa facilitates digital implementation by providing comprehensive synthesis and place-and-route capabilities for both top-level hierarchical designs and block-level executions. Its alignment with signoff tools for STA timing and DRC offers tape-out quality correlation, which minimizes design closure challenges while ensuring peak performance, power efficiency, and area optimization (PPA). With its out-of-the-box performance, Aprisa enables physical designers to streamline each phase of the place-and-route process, accelerating their time-to-market. The unified architecture and shared analysis engines within Aprisa guarantee outstanding timing and DRC correlation throughout implementation stages and with signoff tools, significantly cutting down on the required flow iterations and engineering change orders (ECOs). As a result, this innovative approach ultimately enhances both productivity and design quality in complex projects.
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L-Edit Photonics
Create your photonic integrated circuit within a layout-focused workflow that allows designers to utilize either a drag-and-drop interface or a script-based approach. Both methods are facilitated by a comprehensive custom IC design layout editor, which also manages the physical verification and tape-out stages. L-Edit Photonics allows for rapid photonic design creation through its intuitive drag-and-drop functionality, eliminating the need for coding. Upon finalizing the design, a netlist can be generated to support photonic simulations. The PIC design is entirely integrated within an IC layout editor, enabling users to develop layouts without writing any code, thus supporting a layout-centric approach that does not require a schematic. For those who prefer a schematic flow, S-Edit is available as an optional tool. Moreover, a simulation netlist can be produced for input into a photonic simulator, and photonic simulations are seamlessly incorporated through partnerships with various providers. Additionally, multiple foundries offer photonic PDKs to enhance design capabilities. Overall, this comprehensive workflow simplifies the photonic design process while catering to various designer preferences.
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Siemens PowerPro
PowerPro provides an extensive array of features tailored for RTL designers focused on low-power design. It includes power estimation tools applicable to both RTL and gate-level designs, facilitating early power checks that help identify potential power issues during the RTL development phase. Additionally, it incorporates clock and memory gating techniques to enhance power optimization. With highly accurate estimations that remain within 10% of final signoff, PowerPro's technology leverages sophisticated engines to offer a wide range of analytical capabilities. Furthermore, its automatic power optimization process generates low-power RTL seamlessly while ensuring integrated logic equivalence checking. Notably, PowerPro stands out as the only validated low-power RTL generation technology currently available in the market, solidifying its position as a leader in this domain. This unique combination of features not only streamlines the design process but also significantly reduces power consumption in electronic products.
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Company Details
Company:
Siemens
Year Founded:
1847
Headquarters:
United States
Website:
eda.sw.siemens.com/en-US/ic/aprisa/
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