Siemens Aprisa Description
To manage the increasing complexity, a new place and route paradigm is needed to design at advanced process nodes. Aprisa is an advanced physical design platform that focuses on detail-routes for modern SoCs. Aprisa is a RTL2GDSII implementation that offers complete synthesis, place-and route functionality and block-level implementation for top-level hierarchical design. Its tape-out correlation with signoffs tools, for both STA timing and the DRC, reduces design closing and ensures optimal performance and power. Aprisa delivers optimal PPA out-of-the-box. This helps physical designers reduce effort at each stage of the place and route flow and achieve faster times to market. Unified architecture and common analyses engines ensure excellent timing between implementation steps and signoff tools.
Siemens Aprisa Alternatives
Sigrity X Platform
Sigrity X Platform combines innovation and optimization to take you into the future. Unlock the key to flawless power and signal integrity in your PCB designs and IC packages, and leap beyond the current limitations of signal integrity technology. Imagine navigating the complexity of electronic design with ease and precision, and exceeding your time-to market targets.
Sigrity X is not just another tool. It unlocks seamless in-design synergy between Allegro X PCBs and IC Packages. Explore a comprehensive set of SI/PI Analysis, in-design Interconnect Modeling, and PDN Analysis tools that will supercharge your performance and ensure your projects meet deadlines and budgets.
Use the Sigrity X Platform to achieve flawless performance and reliability in your next design.
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L-Edit Photonics
Design your photonic integrated system in a layout-centric flow. Designers can implement their designs using either drag-and drop or script-driven methodologies. Both are done in the same custom IC layout editor which drives the physical verification process and tape-out. L-Edit Photonics allows the creation of a fast photonic design by using drag-and-drop in an IC Layout Editor, without having to code a single line. Once the design has been completed, a netlist for photonic simulation can be extracted. PIC design with a complete IC Layout Editor. Create a layout in a single click. Supports a flow of design that is layout-centric, where schematics are not required. S-Edit allows for a schematic flow. A simulation netlist is a useful input to a photonic sim. Integration with our partners allows us to support photonic simulation. Multiple foundries offer photonic PDKs.
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Siemens PowerPro
PowerPro offers the most comprehensive set of features to RTL designers to "design-for-low-power". It offers power estimations for both RTL- and Gate-level designs. Early power checks are available to quickly identify power issues during RTL design development. Clock and memory gating is also offered to optimize the design. PowerPro offers the most comprehensive set of features to RTL designers to "design-for-low-power". It provides power analysis for RTL and gate level designs, early power checking to quickly identify power issues during RTL design, and clock and Memory gating for optimizing the design for power. PowerPro provides highly accurate estimations within 10% of the signoff. This technology is based on advanced engines which enable a wide range of analysis capabilities. PowerPro's automatic optimization produces low-power RTL with integrated logic equivalence checks. PowerPro's automatic power optimization is the only low-power RTL technology on the market that has been proven.
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Oasys-RTL
Oasys RTL addresses the need for increased capacity, faster runtimes and improved QoR by optimizing on a higher abstraction level and using integrated floorplanning capabilities. Oasys RTL provides better results by enabling floorplanning and fast optimization iterations. Power-aware synthesis includes support for multithreshold libraries and automatic clock gating. Oasys RTL inserts the appropriate level-shifters, isolation cells and retention registers based on the power intent defined in the UPF. Oasys RTL can create a floorplan from the design RTL by using design dataflow, timing, power, area and congestion constraints. It takes into account regions, fences and blockages as well as other physical guidance by using the advanced floorplan-editing tools. It also automatically places macros and pins.
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Company Details
Company:
Siemens
Year Founded:
1847
Headquarters:
United States
Website:
eda.sw.siemens.com/en-US/ic/aprisa/
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