I think most are missing the politics.

This is surprising, coming as it does on the heels of Microsoft's refusal to comply with the U.S. Federal court order to hand over overseas held emails.

So I will spell out some of the political consequences here.

The service closure forces a service switch on the remaining people who were using non-Microsoft MSN clients and thus avoiding the Guangming, which operates the Chinese version of Skype, which has been modified "to support Internet regulations", which is to say The Great Firewall of China. If these users want comparable services, the only comparable one now available to them is Tencent’s QQ messaging software, which from the start has been designed "to support Internet regulations". So there are no longer any "too big to shoot in the head" options which do NOT "support Internet regulations".

So really the only people who care about this will be Chinese dissidents who want to communicate with each other using an encrypted channel through a server inaccessible to the Chinese government, and any journalists seeking an encrypted channel whereby they can move information out of China without having to have a government approved satellite uplink handy, or a willingness to smuggle out data storage some other way.

Hardkernel wasn't using Broadcom SoC anyway?

The linked article makes it pretty clear they were basing it on Samsung Exynos SoCs - who *cares* whether or not Broadcom would source them parts, if they weren't even using Broadcom in their design?!? This is like using a Motorola 6502 in a design, and then claiming that Intel wouldn't sell you 8008's ... what the hell?

I don't know about rural Japan, but I found the OSM data far better when I visited Tokyo a few months ago. Google didn't know building names and placed a load of things that we were trying to visit a few blocks away from where they actually were. This was very frustrating as the web site that we were using to find vegetarian restaurants used Google maps - we spent half an hour one lunchtime walking in the wrong direction, because we'd come to a junction and, according to the Google map needed to turn left and would then see our destination on the right. It turned out, when we eventually found it, that we should have turned right.

I use OSMAnd on my phone[1], but my girlfriend recently bought a Windows Phone and I've been very impressed with Nokia's mapping app (I actually like a lot of what Microsoft's done with Windows Phone 8, but it's a strange mix of very polished and well-designed UI parts and completely unfinished parts with missing features). It's good to see more competition with Google maps, which is becoming increasingly entrenched in spite of the fact that the UI is pretty poor in many regards and the mapping data is terrible. For example, here they're missing (or have in the wrong places) most of the cycle paths, which ends up with people regularly getting lost if they rely on Google, in spite of the fact that all of this data is in OpenStreetMap.

[1] For me, it's the killer app for Android. Offline maps, offline routing, and open source backed by high-quality mapping data from OpenStreetMap. I use the version from the F-Droid store, which doesn't have the limitations of the free version from Google Play and it's one of the few open source apps that I've donated money to.

Remember when the SoundBlaster Live! came out and Creative Labs were telling you that it had as much processing power as a Pentium 166MHz MMX, dedicated entirely to sound processing? Well, it turns out that now you can have far more CPU power than that dedicated entirely to sound processing without custom hardware...

They're a pain for people on both sides of the ISA.

The compiler has to find an instruction that can run after the branch. This is normally trivial for calls, but for conditional branches within a function it's often difficult to find an instruction that you can put there. It has to be one that is either from before the jump (or in both basic blocks after the jump), but that the branch doesn't depend on (because it's executed after the branch instruction). This means that you quite often end up padding the delay slots with nops, which bloats your instruction cache usage. On a superscalar implementation this is the only cost, but on a simple in-order pipeline it's also a completely wasted cycle.

On the other side, it's a pain to implement. It made sense for a three-stage pipeline in the original MIPS, because you always knew the next instruction to fetch. A modern simple pipeline is 5-7 stages though, so your branch is still in register fetch (if there) by the time the delay slot is needed. It doesn't buy anything and it means that, if you're doing any kind of speculative execution (even simple branch prediction, which you really need to do to get moderately good performance) then you have an extra dependency to track - you can't just use the branch as the marker and flush everything after it, you need to do some reordering. In a superscalar implementation, you need to do even more complex things in register renaming to make it work.

It's only "safe" if you 1) trust that the machine to which you're connecting restricts the ability to bind to ports under 1024 (not guaranteed), and that the only people running processes on the machine in question are either trustworthy or are restricted from running programs that bind to those ports (not guaranteed), and that the system services you care about have ports under 1024 (not guaranteed).

And what guarantees that a "system service" (whatever that might mean) has a port under 1024? Perhaps a better scheme for determining whether to trust a service is called for here - one that would probably obviate the need for "privileged ports".

One would hope that services that trust untrustworthy guarantees would be in the minority; in the best of all possible worlds, they would be completely non-existent.

Good. Ideally, nobody would trust them, and claims such as "It prevents regular user programs from masquerading as system services, which usually sit below port 1024." would be treated as the uninteresting claims that they are.

"CISC functionality" is the ability to execute a given CISC instruction set with acceptable performance. Transistors can be used in several different ways to achieve that, and you can choose to use fewer transistors in one place on a chip in favor of more transistors in another place, and if that choice means you still get better overall performance executing the same instruction set, that choice is a good one.

Again, as long as the full instruction set can be executed (even if some of it is executed by trap code), you don't have a subset. You may happen to execute some functions slower, and other functions faster, but if the net result is faster execution of the code actually run on the machine, you have a better implementation.

Smart people add registers iff they're sufficiently useful that it's worth either increasing the die size or taking transistors away from other functions.

For existing architectures, the reason they don't do it is that it would require changes to the instruction format, which, for most instruction set architectures, would be a royal pain. For x86, they (AMD, to be specific) could and did add Yet Another Prefix to double the number of registers as the instruction set already had a tradition of adding prefixes. For ARM, they were already introducing a 64-bit variant of the instruction set, and didn't have to maintain binary compatibility. For, for example, System/3x0, you'd have to add prefixes to an instruction set lacking prefixes, or somehow use opcode bits to refer to additional registers. If somebody were to design a brand new CISC architecture (in an era where we're not designing many new instruction set architectures at all), they could design one with 32 GPRs.

No idea. I don't know if the instructions for computing PC-relative addresses in an ISA without an architectural PC are patentable. They also exist in RISC V (not sure which came first), so if they do then it's going to be a problem for Kriste et al. Nothing else in there is especially novel: like ARMv8, it's a nicely designed compilation target, but it doesn't do anything that's especially exciting.

I didn't look at the floating point stuff in much detail, so there may be something there, although the biggest changes in recent versions of the MIPS specs have been that they're more closely aligned with the IEEE floating point standards, so it's hard to imagine anything there.

The biggest difference between MIPS64r6 and ARMv8 is that the MIPS spec explicitly reserves some of the opcode space for vendor-specific extensions (we use this space, although our core predates the current spec - it's largely codifying existing opcode use). This allows, for example, Cavium to add custom instructions that are useful for network switches but not very useful for other things. ARMv8, in contrast, expects that any non-standard extensions are in the form of accelerator cores with a completely different ISA. This means that any code compiled for one ARMv8 core should run on any ARMv8 implementation, which is a big advantage. With MIPS, anything compiled for the core ISA should run everywhere, but people using custom variants (e.g. Cisco and Juniper, who use the Cavium parts in some of their products) will ship code that won't run on another vendors' chips.

Historically, this has been a problem for the MIPS ecosystem because each MIPS vendor has forked GCC and GNU binutils, hacked it up to support their extensions, but done so in a way that makes it impossible to merge the code upstream (because they've broken every other MIPS chip in the process) and left their customers with an ageing toolchain to deal with. I've been working with the Imagination guys to try to make sure that the code in LLVM is arranged in such a way that it's relatively easy to add vendor-specific extensions without breaking everything else.

Imagination doesn't currently have any 64-bit cores to license, but I expect that they will quite soon...

Assuming that your code doesn't do anything that is vaguely MIPS specific. If it is, then there is little benefit in using MIPS32r2 now - ARMv7 is likely to be closer than MIPS32r2 to MIPS32r6 in terms of compatibility with C (or higher-level language) source code compatibility.

Basically, because the MIPS ISA sucks as a compiler target. Delay slots are annoying and provide little benefit with modern microarchitectures. The only way to do PC-relative addressing is an ugly hack in the ABI, requiring that every call uses jalr with $t9 in the call, which means that you can't use bal for short calls. The lwl / lwr instructions for unaligned loads are just horrible and introduce nasty pipeline dependencies. The branch likely instructions are almost always misused, but as they're the only way of doing a branch without a delay slot there's often no alternative.

There's no price yet because they're giving away the first production run to people who are going to do interesting things with them. Unfortunately, this is a really bad time to do anything MIPS related (and I say this as someone who hacks on a MIPS IV compatible softcore and the LLVM MIPS back end). Imagination has just released the MIPS64r6 and MIPS32r6 specs. These are the biggest revisions to the MIPS ISA since MIPS III, which introduced 64-bit support. They've removed a load of legacy crap like the lwr and lwl instructions and the branch-likely instruction family and added things like compact (no delay slot) branch instructions, the requirement that hardware supports unaligned loads and stores (or, at least, that the OS traps and emulates them), and added much better support for PC-relative addressing. The result is a nice ISA, which is not backwards compatible with MIPS32r2 or MIPS64r2, the ISA that these boards use. Any investment in software for MIPS now is going to be wasted when products with the new ISA come out.

For building big C++ projects, as long as the disk (yay SSDs!) can keep up, you can throw as many cores as you can get at the compile step and get a speedup, then sit dependent on single-thread performance for the linking. I got a huge speedup going from a Core 2 Duo to a Sandy Bridge quad i7, then another noticeable speedup going to a Haswell i7 in my laptop. The laptop is now sufficiently fast that I do a lot more locally - previously I'd mostly work on a remote server with 32 cores, 256GB of RAM (and a 3TB mirrored ZFS array with a 512GB SSD for ZIL and L2ARC), but now the laptop is only about a factor of 2 slower in terms of build times, so for developing individual components (e.g. LLVM+Clang) I'll use the laptop and only build the complete system on the server.

There are several nice features of a landline, but they can't (in the UK, at least) compete on price. The line rental alone for a landline costs more than I spend on calls on my mobile (pre-pay, no contract, no monthly fees). Calls from my mobile are 3p/minute, a landline is £16/month. I'd need to spend almost 9 hours on the phone each month before I spent as much on my mobile as a landline would cost me before I even made any calls. And then, for the kicker, the calls from the landline cost 9p/min (+15p setup) for calls to other landlines or 12p/min (+15p setup) for calls to mobiles. There's no possible justification for calls from the landline costing 3-4 times as much as calls from the mobile on top of the extortionate line rental. If I wanted to pay BT even more, for another £3 I could get free evening and weekend calls to landlines, but calls to mobiles would still be the same price. For £7.50 on top of the line rental, I'd get free calls to landlines, and calls to mobiles would only be twice the cost of my mobile. Almost everyone I call has a mobile though, so in exchange for paying BT an amount equivalent to about 12 hours of calls on my mobile per month, I could then pay double per minute what I pay for calls on my mobile with no line rental.

I enjoyed that article, but it's worth noting that vi actually is standard.