Comment Yay! (Score 1) 1
Glad we finally got the tapeout sent!
Submission + - Libre-SOC fully Libre/Open Hardware 180nm OpenPOWER ASIC submitted to IMEC MPW (openpowerfoundation.org) 1
lkcl writes: Libre-SOC's NLnet-funded entirely Libre 180nm ASIC, which can be replicated down to symbolic level GDS-II with no NDAs of any kind, has been submitted to IMEC for fabrication. It is the first wholly-independent Power ISA ASIC outside of IBM to go Silicon in 12 years. Microwatt went to Skywater 130nm in March however it is also developed by IBM, as an exceptionally well-made Reference Design, which Libre-SOC used for verification.
Whilst it would seem that Libre-SOC is jumping on the chip shortage innovation bandwagon, it has actually been in development for over 3 and a half years so far: it even pre-dates the OpenLane initiative, and has the same objectives: full automated HDL to GDS-II, full transparency and auditability with Libre VLSI tools Coriolis2 and Libre Cell Libraries from Chips4Makers.
With EUR 400,000 in funding from NLnet and an application to NGI Pointer under consideration, the next steps are to continue development of Draft Cray-style Vectors (SVP64) to the already Supercomputer-level Power ISA, under the watchful eye of the upcoming OpenPOWER ISA Workgroup.
Whilst it would seem that Libre-SOC is jumping on the chip shortage innovation bandwagon, it has actually been in development for over 3 and a half years so far: it even pre-dates the OpenLane initiative, and has the same objectives: full automated HDL to GDS-II, full transparency and auditability with Libre VLSI tools Coriolis2 and Libre Cell Libraries from Chips4Makers.
With EUR 400,000 in funding from NLnet and an application to NGI Pointer under consideration, the next steps are to continue development of Draft Cray-style Vectors (SVP64) to the already Supercomputer-level Power ISA, under the watchful eye of the upcoming OpenPOWER ISA Workgroup.
Submission + - Libre-RISC-V 3D CPU/GPU applying for EUR 400,000 worth of NLNet Grants (google.com)
lkcl writes: The Libre RISC-V Hybrid CPU/GPU, previously reported on /., is applying for eight additional grants from the NLNet Foundation, totalling EUR 400,000. Details on each Grant Application are on the newly-opened RISC-V Community Forum.
The general idea is to kick RISC-V into a commercially-viable mass-volume high gear by putting forward funding proposals for NEON/SSE-style Video Acceleration to be upstreamed for use by ffmpeg, vlc, mplayer and gstreamer; hardware-assisted Mesa 3D (a port of the RADV Vulkan Driver to RISC-V), and a hardware-accelerated OpenCL port to RISC-V. This all in a "Hybrid" fashion (a la NEON/SSE) as opposed to the "usual" way that 3D and Video is done, which hugely complicate both software drivers and applications debugging.
In addition, the Libre RISC-V SoC itself is applying for grants to do a gcc port supporting its Vectorisation Engine including auto-vectorisation, and, crucially, to do an entirely Libre-licensed ASIC Layout using LIP6.fr coriolis2, working in tandem with Chips4Makers to create a 180nm commercially-viable single-core dual-issue test ASIC.
The process takes approximately 2-3 months for approval. Once accepted, anyone may be the direct (tax-deductible) recipient of NLNet donations, for sub-tasks completed. Worth noting: Puri.sm is sponsoring the project, and, given NLNet's Charitable Status, donations from Corporations (or individuals) are 100% tax-deductible.
The general idea is to kick RISC-V into a commercially-viable mass-volume high gear by putting forward funding proposals for NEON/SSE-style Video Acceleration to be upstreamed for use by ffmpeg, vlc, mplayer and gstreamer; hardware-assisted Mesa 3D (a port of the RADV Vulkan Driver to RISC-V), and a hardware-accelerated OpenCL port to RISC-V. This all in a "Hybrid" fashion (a la NEON/SSE) as opposed to the "usual" way that 3D and Video is done, which hugely complicate both software drivers and applications debugging.
In addition, the Libre RISC-V SoC itself is applying for grants to do a gcc port supporting its Vectorisation Engine including auto-vectorisation, and, crucially, to do an entirely Libre-licensed ASIC Layout using LIP6.fr coriolis2, working in tandem with Chips4Makers to create a 180nm commercially-viable single-core dual-issue test ASIC.
The process takes approximately 2-3 months for approval. Once accepted, anyone may be the direct (tax-deductible) recipient of NLNet donations, for sub-tasks completed. Worth noting: Puri.sm is sponsoring the project, and, given NLNet's Charitable Status, donations from Corporations (or individuals) are 100% tax-deductible.
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