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Comment Re:Arr (Score 1) 147

1. The Iowa class battleship has a foot thick armor on the hull. WW2 ships used armor that was sometimes even thicker. Washington class had 16 inch armor for instance.

ARMOR BELT != HULL.

REGARDLESS YOU CLAIMED SUCH HULLS ARE COMMON, THEY DON'T EXIST, MUCH LESS COMMONLY. STOP TRYING TO BACKTRACK. HOW MUCH DID YOU PAY FOR THAT UID?

2. cargo ships conventionally have to have accommodations for people. The entire ship, other than the engine room(s), could be one big vault, with the entire top being a doorway to allow access to the interior, much like the old space shuttle. It would be no more difficult to load or unload than existing cargo ships.

15 PEOPLE AND THEIR LIFE SUPPORT SYSTEMS ARE AN INSIGNIFICANT CONSIDERATION IN AN INTERMODAL SHIP DESIGN.

DOORS WHICH OPEN LIKE THE SPACE SHUTTLE, YET ARE HUNDREDS OF FEET LONG AND 12" THICK WOULD BE AN ENGINEERING MARVEL, WOULD COST MORE THAN THE LOSS OF DOZENS OF PIRATE RAIDS, COST CARGO CAPACITY, AND PROTECT AGAINST A THREAT WHICH DOES NOT EXIST.

3. Presumably, there are reasons why they want to run autonomous ships in the first place. If it isn't profitable, obviously they won't do it. I was simply suggesting that looking at things from a perspective of ships that are always designed for accommodating at least a few human passengers may create limitations on what designs are practical, and if we drop those assumptions, other possibilities may surface.

HUMANS ON THE SHIP DOES NOT PREVENT ARMOR TODAY. FULL STOP. ARMOR DOES NOT EXIST BECAUSE IT PROTECTS AGAINST A NON THREAT.

4. Actually, I thought generally pirates made their money by robbing the people on the ship... but then I wasn't the one who initially suggested that these ships would be vulnerable to piracy. I was only proposing that it may be possible to mitigate such vulnerability, assuming it it were to exist in the first place, by incorporating design changes into such a vessel that would not be practical if the vessel needed to carry a human crew.

THEY TAKE HOSTAGES FOR RANSOM. SELLING 100,000 PAIRS OF NIKE SHOES IS NOT PRACTICAL WHEN YOU'RE RAIDING WITH SPEEDBOATS, NOR IS IT PROFITABLE EVEN IF YOU HAD CARGO ROOM. CHINA SHIPS TOILET PAPER TO THE US. TOILET PAPER.

Comment Re:Arr (Score 1) 147

1 - NOBODY HAS EVER HAD 12" THICK HULLS DESPITE YOUR CLAIM

2 - YOUR "VAULT" CONCEPT OF A CARGO SHIP IGNORES HOW CARGO SHIPS ARE LOADED AND UNLOADED.

3 - YOUR "SACRIFICE CARGO CAPACITY FOR ARMOR PLATING" CONCEPT IGNORES THE ECONOMICS OF THE FREIGHT INDUSTRY. THE NAME OF THE GAME IS VOLUME AND A SHIP WHICH CAN'T DELIVER THAT IS NOT PROFITABLE TODAY, AND A 15 MEMBER CREW ISN'T THE REASON.

"Sed ut perspiciatis unde omnis iste natus error sit voluptatem accusantium doloremque laudantium, totam rem aperiam, eaque ipsa quae ab illo inventore veritatis et quasi architecto beatae vitae dicta sunt explicabo. Nemo enim ipsam voluptatem quia voluptas sit aspernatur aut odit aut fugit, sed quia consequuntur magni dolores eos qui ratione voluptatem sequi nesciunt. Neque porro quisquam est, qui dolorem ipsum quia dolor sit amet, consectetur, adipisci velit, sed quia non numquam eius modi tempora incidunt ut labore et dolore magnam aliquam quaerat voluptatem. Ut enim ad minima veniam, quis nostrum exercitationem ullam corporis suscipit laboriosam, nisi ut aliquid ex ea commodi consequatur? Quis autem vel eum iure reprehenderit qui in ea voluptate velit esse quam nihil molestiae consequatur, vel illum qui dolorem eum fugiat quo voluptas nulla pariatur?"

Comment Re:Arr (Score 1) 147

Not only did I never claim battleships and their ilk had 1" thick hulls, you're confusing the concept of hull thickness with armor belt thickness.

Unless you can learn to read this is the end.

Container ships, which is what we are talking about, do not and never have had anything within an order of magnitude of 12" hulls, despite your claims.

Comment Re:How can this work with European smart cards? (Score 1) 181

Unlike the US, European cards generally have a chip in them and use a nonce based protocol. So skimming the interaction with the ATM is not going to buy very much. Not the secret in the chip. Maybe the extra number written on the back if it has a camera.

So what was the point?

But the EU cards also have mag stripes for compatibility in the Americas (and Pacific, and other places). So the card is skimmed in the EU and used either online or overseas.

Comment Re:No EPUB - No Thanks (Score 1) 87

The e-ink Kindles can be jailbroken and run little apps, including epub readers.

But doing that, IMHO, throws the baby out with the bathwater.

My favorite feature of the Kindles is that I can send books to them via Calibre and Wifi as they have their own dedicated email address solely for delivering books.

Comment Re:It does almost nothing very very fast (Score 1) 205

Ah, OK, so it is more or less the latest version of ASaP/ASaP2. I just made a post up-thread about my memory of ASaP. It looked interesting, but as you point out, it has some real practical issues.

At the time we spoke with them, it sounded like whenever you loaded an algorithm chain, you had to map it to the specific chip you were going to run it on, even, to account for bad cores, different core speeds, etc. Each core has a local oscillator. Whee...

Comment Re:I guess this is great (Score 1) 205

I'm familiar with Dr. Baas' older work (ASaP and ASaP2). He presented his work to a team of processor architects I was a part of several years ago.

At least at that time (which, as I said, was several years ago), one class of algorithms they were looking at was signal processing chains, where the processing steps could be described as a directed graph of processing steps. The ASaP compiler would then decompose the computational kernels so that the compute / storage / bandwidth requirements were roughly equal in each subdivision, and then allocate nodes in the resulting, reduced graphs to processors in the array.

(By roughly equal, I mean that each core would hit its bottleneck at roughly the same time as the others whenever possible, whether it be compute or bandwidth. For storage, you were limited to the tiny memory on each processor, unless you grabbed a neighbor and used it solely for its memory.)

The actual array had a straightforward Manhattan routing scheme, where each node could talk to its neighbors, or bypass a neighbor and reach two nodes away (IIRC), with a small latency penalty. Communication was scoreboarded, so each processor ran when it had data and room in its output buffer, and would locally stall if it couldn't input or output. The graph mapping scheme was pretty flexible, and it could account for heterogenous core mixes. For example, you could have a few cores with "more expensive" operations only needed by a few stages of the algorithm. Or, interestingly, avoid bad cores, routing around them.

It was a GALS design (Globally Asynchronous, Locally Synchronous), meaning that each of the cores were running slightly different frequencies. That alone makes the cores slightly heterogeneous. IIRC, the mapping algorithm could take that into account as well. In fact, as I recall, you pretty much needed to remap your algorithm to the specific chip you had in-hand to ensure best operation.

The examples we saw included stuff familiar to the business I was in—DSP—and included stuff like WiFi router stacks, various kinds of modem processing pipelines, and I believe some video processing pipelines. The processors themselves had very little memory, and in fact some algorithms would borrow a neighboring core just for its RAM, if it needed it for intermediate results or lookup tables. I think FFT was one example, where the sine tables ended up stored in the neighbor.

That mapping technology reminds me quite a lot of synthesis technologies for FPGAs, or maybe the mapping technologies they use to compile a large design for simulation on a box like Cadence's Palladium. The big difference is granularity. Instead of lookup-table (LUT) cells, and gate-level mapping, you're operating at the level of a simple loop kernel.

Lots of interesting workloads could run on such a device, particularly if they have heterogenous compute stages. Large matrix computations aren't as interesting. They need to touch a lot of data, and they're doing the same basic operations across all the elements. So, it doesn't serve the lower levels of the machine learning/machine vision stacks well. But the middle layer, which focuses on decision-guided computation, may benefit from large numbers of nimble cores that can dynamically load balance a little better across the whole net.

I haven't read the KiloCore paper yet, but I suspect it draws on the ASaP/ASaP2 legacy. The blurb certainly reminds me of that work.

And what's funny, is about 2 days before they announced KiloCore, I was just describing Dr. Baas' work to someone else. I shouldn't have been surprised he was working on something interesting.

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