My workplace is primarily a Verilog shop (FPGA design only, no ASICs), though we're forced to use VHDL on occasion when a piece of IP is written in it, or to interface with Xilinx's EDK toolchain, which is mostly written in VHDL. We haven't switched to using System Verilog, but we do attempt to stick to the Verilog 2001 style coding, instead of the Verilog 95 standard. Verilog 95 makes the same code significantly longer and more annoying to change. Things like generate statements and parameter passing have been in place in Verilog since that standard, and all the toolchains that we've used (Xilinx, Altera, Synplicity) support it, albeit only fully since the latest ISE 11 software release in Xilinx's case.
Having only done a minimal amount of VHDL, I can tell you that I can't stand it due to the excessive verbosity that is required to do anything in the language, though one of my wishes is that Verilog removed implicit variable declaration, as occasionally a typo will cause a design not to function correctly, which as mentioned will not happen in VHDL. A compiler option for that one would be nice ;).
To answer your question as to which you should teach, I would go with Verilog as I find it's easier to use (which may be bias on my part, having used it far more than VHDL), but make sure that you teach "clean" ways of writing the HDL. I've seen a fair bit of excessively verbose, hard to read Verilog code (a lot of the code Xilinx provides for their parts is like this) which could be a lot cleaner if it was written differently.
Another thing that I think would be a useful thing to go over is each step of the FPGA build and what it's actual purpose is. What is the output of the synthesizer? What is the output of the mapper?