First off you bottleneck on the SATA portion of the chip-set at 6Gbps. The SATA over nvme m.2 operated by bridging the SATA controller data stream over a pci-e link. Secondly nvme is is an entirely different block layer, which the kernel expect to be directed to the drive controller. A controller in the middle is going to double latency and minimum and would have to redesigned for the different protocol. Possible but still I ask why?