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Silicon Graphics

R12K Debuts 40

Mike Holve, the guy with the cool website a lot of us have read, wrote in with a link to an SGI Press Release about the company using the new R12000 (R12K) processor running at 300 MHz in its Octane workstations. The chip is binary- and pin- compatible with the R10K, and from the press release, appears to be relativley inexpensive. Hey, I can dream, can't I? If anyone sees a press release about the actual chip, submit it and I will be sure to update the article. Update: 02/22 07:34 by J :Still no sign of a press release, but thanks to mmoore, we have a nice license plate mask.
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R12K Debuts

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  • .. tops out at 64 CPUs. The base config, which costs just under a million dollars last I checked, comes with 16 CPUs. I forget how many gigabytes of RAM come standard. (Either two or four.)

    - A.P.

    "One World, One Web, One Program" - Microsoft Promotional Ad

  • I have two SGI Indy's, been a big fan of the Indy since it was released and I scrounged together enough cash to get an entry-level system which I've progressively upgraded over the years.

    Where's a good place to buy 2nd hand SGI gear these days? I've considered getting an O2, but I figure if there is a cheap resource for Indigo2's I could always just go that route too...

  • >With IA64, Intel may finally catch up to the Rxk,
    >UltraSparc, and Alpha chips. Perhaps. But we'll
    >have to wait for SGI or HP to make a machine that
    >isn't bogged down by its own bus architecture.

    What are you talking about? I can't think of a single SGI machine that has bus/IO bottleneck issues. Even the new Visual Workstation has a new superwide bus that can easily handle a mere Xenon.
  • by mholve ( 1101 )
    Come on, now. Those CPUs just keep on scaling. You can easily have 128 out of the box, 256 if you ask nicely. The government has a box with over 6,000 MIPS CPUs running... How much do you want?!
  • The math on the MIPS chips will make anything Intel makes look like roadkill, especially the R10/R12K chips.
  • by mholve ( 1101 )
    You're completely missing the point.

    How many Celerons can you pop into a box? Now, how many MIPS? Intel can't shake a stick at SGI's SMP. Not to mention that you can't compare a Celeron to an R12K to begin with!

    I know what you're saying, or trying to - but you're comparing two totally different ends of the design spectrum. Celerons are entry level CPUs. R12Ks are top of the line. One is meant for low-cost home use the other for seriously heavy duty SMP machines crunching hard numbers, which 160 Celerons couldn't keep up with.

  • by mholve ( 1101 )
    I hate to say "I told you so..." ;>

    Very good news indeed. As if the Octane machines aren't already totally kick-ass, this announcement comes up.

    Someday I might trade in my Indigo2 for an Octane, but even used - an entry level Octane is around $18K, and that's not from SGI, so the trade-up credit of "up to" $7,500 means nada to me (unless of course, I bought the Octane from SGI - way too expensive). Besides, I totally love the Indigo2, especially for 3D (it's a High Impact - realtime 3D!) and video. But some day... Hey, we can all dream, right? :)

    Thanks Justin!

    P.S. Keep an eye out for a new SGI/Linux page I'm working on. Bunches of cool stuff, especially for you SGI and Linux owners out there. (links, info, pre-compiled binaries, etc.)

  • Aww, don't apologize.

    More opinions and answers are always good.

    For what it's worth, there was nothing there as I posted either... We need a realtime Slashdot! :)

  • I got my equipment and also highly recommend Reputable Systems []. Greg Douglas is a great person to deal with and I'm a very happy customer.
  • by mholve ( 1101 )
    Everyone is entitled to their opinions, but come on! I hope you're not seriously suggesting that a Linux system can handle anything even remotely like the SGI systems can as far as video, 3D and intense scientific analysis? This is not a criticism of Linux per se - but what Linux runs on. Another thing you need to look at are the apps that are available for SGI that aren't on Linux. I'm sure Hollywood had it's reasons for using SGI equipment and related software such as Houdini, Pirahna, Alias, Avid and others - it's because SGIs did it fast, did it repeatedly and did it reliably.

    Now, once the port of Linux to MIPS CPUs (or perhaps, more specifically - SGI hardware) is done - and is complete - then you might have an argument - but look also at the hardware that SGI has... You're comparing apples to oranges in an absurd comparison to begin with.

    P.S. My SGI runs the GIMP a hell of a lot faster than my Intel box running Linux, thanks...

  • Now will it crunch RC5 keys faster then say an
    intel pentium 200?
  • The key word being 'relatively'. :-)

  • also sells used SGI equipment for a fairly good price & offers a 6 month warranty. I haven't dealt with them personally, though.


  • Well, a lot of people use it. I suppose that's because they used Patterson/Hennesy books in their CPU design class at school.

    I think it does well in the embeded market because the R4x00 is really damm cheap compaired to any other embeded CPU with similiar performance (or at least it was two years ago, when many of todays products were designed). Go look at the NEC(?) VR4600 prices and tell me the 120Mhz i960 is price competatave! Remember the 4600 has lots of stuff integrated into it as well (not as much as the 68F333, but the 68F333 only runs at 25Mhz!, nor as much as the Cyrex MediaGX, but the MGX is way to costly to see in a cell phone! The MGX's integrated parts are also mostly PC desktop/notebook specific)

    IMHO, MIPS is horribly miscast as an embedded architecture. Because it is so streamline, the code density is horrible.

    Um, what are you trying to say here? As far as I know the MIPS code density is roughly the same as the SPARC, somewhat better then the ALPHA, around the same as the i960. It's only worse then the CISCs, and the x86 CISCs are gennerally to costly and slow for most embeded applications, so that leaves the 68k and CPU32, both of which are fairly slow compaired to a R4x00 (or an R3000!), or any other modernish RISC.

  • You are talking about compiled code, I am talking
    about hand-tuned code. SGI has good compilers, but
    they are close to what you can get from the
    architecture. You can't get much impovement with
    hand-written assembly on a MIPS (or Alpha) because
    they are so simple. You can do much better on a
    SPARC or PPC

    So the MIPS sucks because you don't have to hand-code assembly to get good performance? Does that mean the BMW M3 sucks because it gets good 0-60 times with it's automatic transmision?

    I've hand coded SPARC assembly, and while I can do better then gcc, I don't beat Sun's compiler. Unless I happen to be using the VIS instructions (only on the UltraSPARC, and not a part of SPARC V9). Does that mean the SPARC sucks too now?

    NOTE: the SPARC and MIPS are both quite simple ISAs, but to get good performance on a modern implmentataion of either you need to pay careful attention to the grouping rules, and data dependencies so your SuperSPARC can issue as close to four instructions per cycle as possable, or your Ultra as close to five as possable (sorry, I don't recall the MIPS maximum execution rates, nor the max rates for the Alpha's either). It's actually harder to hand code fast assembly for these beasts then it was back on the old 68020! Or many other assorted CISCs. Then again it isn't my job anymore, so maybe I'm just bad at it now.

    Bonus Alpha trivia: the 21264's register rename file is actually two banks of 40 registers each, and if your instruction ends up referencing registers from diffrent banks there is a one cycle penalty. Because these are rename registers they are assigned at runtime, baised on control and dataflow, including effects of mis-prediction. It's basically impossable for a person to figure out how the registers will get renamed, but a really smart compiler could probbably make some good guesses. Not that I have seen a compiler do that mind you, it's just the kind of stuff modern CPUs do that make hand optmising a tripple bitch and a half of a nightmare.

    You are forgeting ARM. ARMs code density is awesome. It's like a spiritual successor to 68K. Not surprisingly, ARM and 68K are ruling the embedded market.

    Ok, I forgot about the ARM. It's code density isn't all that great, what with losing 4 bits to make every instruction conditional (which is cool, but not very dense), and a few more for the shifter that can apply to every ALU output. Even using the DEC Thumb extension (16bit coding) the code density isn't awesum because your back to a two register ISA, and far branches & big constants are a bitch, but yes it does have the best code density of any RISC if you use the Thumb extension. It's also about 20% slower that way, is it not?

    68K is sufficiently fast for most embedded applications. We are talking about people who still use Z80s, for crying out loud.

    Sufficently fast for what? The embeded market is very diverse. The folks replacing complex CAMs in washing machines may be just fine with a Z80 (or Z8!), but the folks doing the PlayStation2 want more comp-u-trons. The PalmPilot has a "mere" 16Mhz 68ECxxx in it, and I hear lots of folks that want something faster! The CPU in my thermostat is probbably just fine as a Z80, but the one controling my ABS breaks would be pushing it as a Z80. A 68K may be just fine to control an elevator, but a PostScript laser printer needs a hell of a lot more CPU! A Z80 in my microwave may be overkill, but you need a lot more then that to control a router with a gigabit backplane. I use to do embedded systems (CoinOp video games), beleve me there are embeded systems, and there are embeded systems! I can come up with a bunch more examples where you want more then a 68K, but I think everyone gets the point.

  • It's good to see that SGI didn't dump the MIPS processor, and there remains that diversity in the market. If everyone abandoned their own processors it would be a bit of a nightmare.

    Heaven help us if we ever end up faced with one (or two) choice(s) of CPU...
    .. the Intel Lada 1.2 or the Intel Lada 1.3....

  • A little insect friend of mine out in the desert
    tells me that the govs' blue mtn. has been using R12k cpus for some time now; for test purposes, of course >:)

    350Mhz Ip31 _me_, baby!

    A little bird that chased the fly to make
    him lunch sez that Sgi's internal sales crapola lists the 300Mhz octane CAD #'s at roughly 30% faster than its previous R10k release (not the 250s) (with Mxe graphics)

    fly on the wall...

    (note: all fly info violates no known NDA's)
  • MIPS is royally screwed now. I mean, what is it?
    If you sell it as a high performance
    "compiler-friendly" architecture, there is Alpha.
    They will be hard-pressed to consistently outperfrom Alpha. An embedded architecture? Well,
    a lot of people use it. I suppose that's because
    they used Patterson/Hennesy books in their
    CPU design class at school. IMHO, MIPS is horribly
    miscast as an embedded architecture. Because it
    is so streamline, the code density is horrible.
  • This is the MIPS swan song. As far as I know
    there is no next generation MIPS CPU in the
    pipeline. The 'Beast' project and the next one
    after that are dead. Or is this the 'Beast'?
    Doesn't look like it. Beast had a target clock of
    around 666Mhz. SGI is probably moving everything to Merced.
    I think the E2k looks interesting to peolple like SGI. CT never posted my translations of the Russian articles, so let me give you a recap. E2K uses a binary recompilator. Something like DEC's FX32!, but with hardware support. Apparently their
    recompiler is easily retargetable. They now
    can compile x86 and SPARC to E2K and run on the
    simulator. They plan to add Merced once the ISA
    is fully disclosed. They claim to have booted Windoze on a SPARC and ran Flight simulator, which
    supposedly won Babayan a bet with Mr. Ross
    (Ross Technologies, creators of HyperSPARC) They can probably add MIPS and any other "legacy" architecture relatively easily...
  • This is not a limitation of any specific CPU,
    but rather of SMP architecture. How many CPU
    do you want to hang out on a single chunk of
    memory? The ASCI machine with several thousands
    MIPS chips was an MPP setup. Sun Enterprise
    with 64 CPUs uses a crossbar to memory and god
    knows what other tricks that have nothing to do
    with CPU itself. You pay dearly for stuff like
  • by muchandr ( 12588 )
    well, its not that bad.

    build a NOW over Myrinet, just 1.2K per node.
    Myricom claims that on PCs, the bottleneck is
    PCI DMA performance. Network faster than
    internal bus. Not bad.
  • by muchandr ( 12588 )
    Of course. Myrinet will set you back $1.2-1.5K
    per node in networking gear.
  • The problem (as far as I understand it) with rc5 on mips isn't that the chips aren't good at it, it's just that too many people have tto much time to optimize Intel rc5 code, and nowhere near as many people are working on the MIPS code.


It is not for me to attempt to fathom the inscrutable workings of Providence. -- The Earl of Birkenhead