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Average Ratings 0 Ratings
Description
Oasys-RTL meets the demand for enhanced capacity, quicker runtimes, elevated quality of results (QoR), and physical awareness by performing optimization at a more abstract level while also incorporating integrated floorplanning and placement features. This tool significantly improves the quality of results by facilitating physical accuracy, efficient floorplanning, and rapid optimization cycles, ensuring timely design closure. Its power-aware synthesis capabilities encompass support for multi-threshold libraries, automatic clock gating, and a UPF-based multi-voltage domain flow. During the synthesis process, Oasys-RTL intelligently inserts the necessary level shifters, isolation cells, and retention registers according to the power intent specified in the UPF framework. Additionally, Oasys-RTL can generate a floorplan directly from the design's RTL by applying dataflow and adhering to timing, power, area, and congestion constraints. It adeptly incorporates regions, fences, blockages, and other physical directives via advanced floorplan editing tools while automatically positioning macros, pins, and pads to optimize the layout. This holistic approach ensures that designers can efficiently manage complex designs and meet stringent performance requirements.
Description
Advance your approach to RF simulation by focusing on the comprehensive design, analysis, and verification of radio frequency integrated circuits (RFICs). Gain assurance through the use of steady-state and nonlinear solvers for both design and verification processes. The availability of wireless standard libraries expedites the validation of intricate RFICs. Prior to finalizing an RFIC, it is essential to confirm IC specifications through RF simulation. These simulations take into account various factors such as layout parasitics, intricate modulated signals, and digital control circuitry. With PathWave RFIC Design, you can perform simulations in both frequency and time domains, facilitating seamless transitions between your designs and Cadence Virtuoso. Achieve accurate modeling of components on silicon chips, and enhance your designs using optimization techniques like sweeps and load-pull analysis. Integration of RF designs into the Cadence Virtuoso environment is streamlined, while the implementation of Monte Carlo and yield analysis can significantly boost performance. Additionally, debugging is made easier with safe operating area alerts, allowing for immediate utilization of cutting-edge foundry technology to stay at the forefront of innovation. This holistic approach to RFIC design not only improves efficiency but also elevates the overall quality and reliability of the final products.
API Access
Has API
API Access
Has API
Integrations
No details available.
Integrations
No details available.
Pricing Details
No price information available.
Free Trial
Free Version
Pricing Details
No price information available.
Free Trial
Free Version
Deployment
Web-Based
On-Premises
iPhone App
iPad App
Android App
Windows
Mac
Linux
Chromebook
Deployment
Web-Based
On-Premises
iPhone App
iPad App
Android App
Windows
Mac
Linux
Chromebook
Customer Support
Business Hours
Live Rep (24/7)
Online Support
Customer Support
Business Hours
Live Rep (24/7)
Online Support
Types of Training
Training Docs
Webinars
Live Training (Online)
In Person
Types of Training
Training Docs
Webinars
Live Training (Online)
In Person
Vendor Details
Company Name
Siemens
Founded
1847
Country
United States
Website
eda.sw.siemens.com/en-US/ic/oasys-rtl/
Vendor Details
Company Name
Keysight Technologies
Country
México
Website
www.keysight.com/us/en/products/software/pathwave-design-software/pathwave-rfic-design-software.html
Product Features
Product Features
PCB Design
3D Visualization
Autorouting
Collaboration Tools
Component Library
Design Rule Check
Differential Pair Routing
Schematic Editor