Scalar design just simply attach more cache... more hits and speculative loads (/MMU) solved it for SPARC/MIPS/Power
The HP research into Dynamo and later the transmeta design concepts showed promise but delivered no product beyond small samples (under 1 million shipped) and yet peoples houses...
I was most excited by dynamo and VLIW (itanium promised so much and delivered so little) LLVM provides some interesting concepts
I would really like Texas Instruments (TI) back in the game as I think a large I and D cache combined with specialised (DSP + crypto) offload engines would blow the socks off the current market...
it will be interesting as intel have a smaller geometry yet the market is with ARMHY but do manufacturers care ?
have fun and power consumption matters !