I would say learn VHDL first - there is a reason for this. VHDL is more stricter in checking for constraints, which has a true basis in hardware.
For example, you cannot read from an output in VHDL, while you can read from outputs in Verilog2K. Also, all the synthesizers (these are the compilers from say Xilinx , and if you move to ASIC design, from Synopsys, etc.) are much more lenient on Verilog - for example assigning to the same wire cannot happen twice (essentially meaning HDL is single static assignment) - in Verilog it is allowed and can generate a multiple driver netlist, leading to a "U" situation.
If you are starting up - I would strongly suggest VHDL - if you are working on stuff, I would say Verilog is much easier. However, it depends on Europe vs USA as well (with a preference for VHDL vs Verilog)