Nope, not phase change. According to Intel XPoint doesn't have any physical changes, only property changes. Some people mentioned electron spins.
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10ghz is what they predicted, XPoint already exists.

Intel said they're unifying memory and storage with this. No more distinction between DRAM and HDs, they're one and the same. Of course other stuff needs to happen first, but that obviously indicates that they expect it to replace DRAM. Actually, the explicitly stated they will make DRAM with it.

"Memristors" are anything with certain meta properties. Assume XPoint fits the theoretical definition of memristor perfectly, you can process and store data at the same time.

Unofficial sources are starting to say that XPoint does not exhibit wear from write cycles and the "1000x more endurance" is normalized to some other metric. If it was normalized against time, then you may expect NAND to last 3-5 years which would put XPoint around 3,000-5,000 years life time. We won't know until more official data or hands-on reviews happen.

DDR3 is about 10ns. If XPoint is 1000x faster than 5us NAND, then it has 1/2 the latency of DRAM. I doubt it, but you can see how it can easily be within a a factor or two.

When you restart your computer without a power down, you still have all that data in memory. Same difference. As for a power down, the only real benefit is it also resets the CPU and other hardware. When the BIOS starts up and copies data from the HD into memory, it already over-writes what was ever there. No changes required. If you want to take advantage of having persistent memory, then you'll need new protocols, but old protocols should continue to work as expected.

shark bait hoo haha - Finding Nemo

2ms is a few magnitudes too high for NAND. Google is returning back latencies of 5us-25us for NAND.

That only works if the newly resulting blocks are the same. If you cause all of the data to shift, then all of the data in the blocks could also shift creating blocks are that not the same. Flipping bits is one thing, but changing length is another.

And you'd both burn our your CPU's SRAM and DRAM in under a year. They're only rated for around 10^16 writes.

TLC VNAND has upwards of 60k cycles, but as low as 5k. Depends on how fast you want it. It's a speed-endurance tradeoff. 60k cycles is about 1/3rd the speed of the 5k cycles. With a non-linear tradeoff that causes diminishing returns on gained speed, there's bound to be a happy medium.

My LCD monitor takes longer than 1sec to turn on. I'm not too concerned. 1sec is "instant" for this class of interactions.

Flipping at bit at 100mhz would burn out your L1 cache's SRAM in one year.

This is where a good manager comes into play. My current and past manager would tell the other departments that if they could not do a good job in a timely fashion, we would do the job.

A programmer's productivity is relatively static. What's important is the quality of the code that allows the programmer to multiply the productivity of others. Code quality becomes very important as each layer of dependencies compounds the complexity of the system. 80/20 rules great until you're 3 dependency layers deep and 0.8^3 is only 0.5.