Micro-Pump is Cool Idea for Future Computer Chips 96
core plexus writes to tell us that Engineers at Purdue University have designed a tiny 'micro-pump' cooling device that can be used to circulate coolant through the channels etched on an individual chip. From the article: "The prototype chip contains numerous water-filled micro-channels, grooves about 100 microns wide, or about the width of a human hair. The channels are covered with a series of hundreds of electrodes, electronic devices that receive varying voltage pulses in such a way that a traveling electric field is created in each channel. The traveling field creates ions, or electrically charged atoms and molecules, which are dragged along by the moving field."
I slightly misunderstood the teaser (Score:5, Informative)
This system works in multiple ways, it has an ionisation pulse that travels along the water lines
The pulse ionizes the water the ionized water is dragged by the pulse
the pulse alters the shape of a small membrane, boosting the pump.
as for the efficiency that being said, it's still work in progress, and they (according to the article) haven't solved leakage problems yet.
From plants (Score:4, Informative)
Link: http://www.cas.muohio.edu/~meicenrd/ANATOMY/Ch9_T
Re:Channels of coolant, or just heat conductor? (Score:4, Informative)
A conductor would have to be thick, which would take up a lot of space.
Moving s liquid with high heat capacity (such as water, which has ENORMOUS heat capacity) means you can move the heat out by transporting the liquid, rather than by conducting the heat THROUGH it. The liquid can then drop off the heat at the heat sink in a leisurely fashion on its way through. Heat only has to move by conduction across distances measured in molecular diameters rather than inches.
Cooling is not the only problem (Score:5, Informative)
For example, one of the assumptions that exists on a semiconductor wafer before it is printed is that it is effectively flat (a typical peak to valley range on a modern wafer within the expected field of a chip is on the order of 175 to 200 nm)
Polishing to that accuracy once structures have been placed on a semiconductor wafer is difficult. Getting a consistent layer of material when you are polishing an uneven surface (uneven due to vias [connections] to the other layers of silicon present) is downright challenging. Another problem with printing transistors on anything but a pure wafer is the issue of reflection. Thin layers of materials on a semiconductor are semi-transparent and not perfectly vertical. Those angled and curved structures produce reflections. Those reflections can cause problems in printing later layers (because of constructive and destructive interference of the light used to expose the photoresist). Those reflections mean that modeling the exposore process of a 3D semiconductor is a VERY challenging task.
Such items are not of concern today, because the later structures placed on the wafer are generally metal lines or capacitors for DRAMs or lenses for image sensors, etc. These are all large and some level of imprecision is acceptable. While variation can cause differnet RC characteristics in metal lines, the timing models in the library or other models can account for this variation. In fact, Matrix Semiconductor has been producing 3D DRAM since about 2004, which shows that heat isn't necessarily the problem, and DRAMs (and memory in general) are a reasonable application for 3D technologies (likely because the capacitors are generally large in relative terms).
Transistors, however, are much more sensitive to variation, and the variation in later polishing used today is too rough for the effective printing of transistors. While I don't doubt that there are situations where the density will be valuable, I think 3D processors and custom chips (in consumer electronics, et al.) are as much an economic issue as a cooling/technical one. (in other words, with my understanding of current roadmaps, you will decrease semiconductor yield to such a degree that 3D may not be economically viable, even if the cooling problem is solved.)
Re:Cooling is not the only problem (Score:1, Informative)
http://en.wikipedia.org/wiki/DRAM [wikipedia.org]
Clarification and more information on 3D (Score:3, Informative)
Specifically related to the issues I mentioned: If you are interested in some of the challenges around flatness, you can learn more about dummy fill that must be added to metal layers, by looking at the layman's version [sematech.org] or a technical description [mit.edu].
With regard to reflection, you can check out a rather old background article [ibm.com] or how anti-reflection layers must be used [future-fab.com] in modern semiconductor manufacturing to reduce problems.
More specific articles on 3D fabrication can probably be found in recent journals (most likely not available online), or if you're not concerned about reading patents, by reading patents from the USPTO (for reasons of US law which you're probably familiar with, I'm not going to search that and provide you any links). There may also be more by searching for Matrix Semiconductor (which I didn't realize at the time of my first posting has been acquired by SanDisk).
Having said that, there is also 3D packaging, which takes various forms. Semiconductor Cubing [nasa.gov] (as it's apparently called) can stack lots of semiconductor devices, but note that these are originally fabricated as single layer chips and then they are bonded together to form a larger block.
More recently (and in real production), 3D packaging is being performed through a System in Package [inemi.org] (SiP) methodology (you may also see this referred to as a 'chip stack' technology). This is distinct from a multi-chip module [ibm.com] (MCM), where the chips are aligned horizontally on the packaging substrate. Today, a SiP is generally a memory module bonded upside down onto a non-memory device (though it can also be used to bond an RF device onto a non-RF device). This form of packaging is receiving attention from SEMATECH [pennnet.com] as well. Further information from SEMI is also available if you Google for "SEMI Forum: Mapping progress in 3D IC integration".
Beyond that, it's again hard, due to the password protected nature of conference materials and journals... but hopefully that's a good set of links to explore.
Not much new, apparently (Score:2, Informative)
I wonder where and how they want to hang the liquid reservoir with the cooling solution. The processor may have to come then with an attached infusion bag like those you get at hospitals.