Comment state machines without timing issues (Score 1) 69
The current way people build finite state machines is using CBL (clocked boolean logic). There is a better way to do this though, called NCL, which i came across while surfing. I studied the pdfs to the degree of being able to sythesize state machines Without Clocks: NEAT!
Two things about introducing NCL to people who do state machines for a living (electrical engineers):
1. No experienced engineer would believe you. I have tried this so many times at the last place i worked (National Semiconductors) I got tired. It is not that they don't know/trust you. Timing is just a *big* problem right now.
2. If they listen long enough to understand what you mean, they get excited (good as a starter if you have really bad news to tell them).
Two things about introducing NCL to people who do state machines for a living (electrical engineers):
1. No experienced engineer would believe you. I have tried this so many times at the last place i worked (National Semiconductors) I got tired. It is not that they don't know/trust you. Timing is just a *big* problem right now.
2. If they listen long enough to understand what you mean, they get excited (good as a starter if you have really bad news to tell them).
