To be fair with Grand Central and Apple's 'blocks' they could probably make some use of such a chip. And it's 'only' a couple of hundred million transistors for a 64-core implementation.

What I see these being is actually more along the line of a Cell SPU, but optimised for low power and inter-core communications. Like Transputer shagged an SPU. As programmers have raised issues with the SPU's 128KB of local RAM, I wonder if the 32KB of local RAM on this design will prove to be an issue in the future.

Might sound silly, but if they could provide an OpenCL front-end to their chip they will make it more desirable, but maybe that would not utilise the features that make their design worthwhile over a low-power GPU.