Comment Easy to work around (Score 5, Interesting) 337
The patent application is very specific about using a ring oscillator to control the processor clock. Most processors use PLL (phase locked loop) devices to control their clock frequency.
Typically only asynchronous CPUs are clocked by free-running ring oscillators. Almost all CPUs on the market, including embedded CPUs, are synchronous designs and they come in fixed speed grades, which makes PLL clocking very attractive.
Even with PLLs you can vary the clock speed, e.g. when you detect that the chip is too hot or when the work load is low the CPU clock can be scaled down in discrete steps.
A ring oscillator provides a non-discrete (continue) frequency range, but on the downside its clock frequency is very unstable compared to PLLs, which is bad for synchronous designs.
There is also prior art: the early MIPS processor implementations had a free running multiplier, which operated as fast as the silicon would allow, even though the rest of the CPU was clocked at a fixed frequency.
In summary: this patent is not worth a lot.
Typically only asynchronous CPUs are clocked by free-running ring oscillators. Almost all CPUs on the market, including embedded CPUs, are synchronous designs and they come in fixed speed grades, which makes PLL clocking very attractive.
Even with PLLs you can vary the clock speed, e.g. when you detect that the chip is too hot or when the work load is low the CPU clock can be scaled down in discrete steps.
A ring oscillator provides a non-discrete (continue) frequency range, but on the downside its clock frequency is very unstable compared to PLLs, which is bad for synchronous designs.
There is also prior art: the early MIPS processor implementations had a free running multiplier, which operated as fast as the silicon would allow, even though the rest of the CPU was clocked at a fixed frequency.
In summary: this patent is not worth a lot.
