Careful with your comments there - DRAM is relatively slow because the capacitors used are tiny, so sensing the charge state is slow. The need to refresh is because it's a capacitor with non-zero leakage. Refresh cycles sometimes will delay normal accesses, but are not the reason that DRAM is slower than SRAM. The speed of memresistor memory reads will depend on the speed of sensing the state, and the speed of writes will depend on the speed of changing the flux.