This is all wishful thinking so I'll cut right to it. IMHO, Intel is on the verge of replacing the rotational magnetic storage medium that we've all come to know and love as the hard drive. Allow me to retort.
In February of 2000, Intel invested in a small startup known as Ovonyx for technology known as "Ovonic Unified Memory". Also known as phase-change memory, this stuff is a non-volatile RAM that uses a chalcogenide glass to store data as a resistance. Read the link presentation for more info.
Getting to the point:
In the beginning, Intel has made no secret of their plans to replace flash with OUM or other promising alternative (with OUM being the undisputed favorite out of the 20 or so current candidates). The development has dragged out for quite some time now and, just this summer, Stefan Lai (Intel's VP of technology) stated that there was "no question" that the technology works but also that it was just too expensive. He then went on to say, "With ovonics, we believe we have an idea how to reduce the costs, but we could not disclose that now. When we are ready to talk about it, the industry will be surprised, I promise you".
They've been remarkably quiet about the timeframe aside from the quote about the technology being pushed back 5 years or more. I think that this was not accurate and here is why:
One analyst, Dan Hutcheson of VLSI Research Corp., predicted that Intel's surprise move to implement a form of strained silicon at the 90-nm node -- slated to move into manufacturing next year exclusively on 300-mm wafers at three Intel fabs -- will reverberate as widely as IBM's 1997 decision to implement copper interconnects at 180-nm design rules.
IBM announced their work in strained silicon years ago but Intel remained skeptical up until their announcement of adoptation for their upcoming 90 nanometer process. So why the about face? Intel remains quiet but I believe that they've adopted strained silicon specifically for use with OUM technology.
Changing gears without deviating from the topic: one of Intel's upcoming wireless-internet-on-a-chip technologies is currently known as Bulverde. From Intel's own outline, this chip contains on-chip NVRAM. They currently do this with flash on the PXA800F so why not carry the technology down to the 90 nanometer process? Well, for one, the Bulverde announcement (see above) seems a little more revolutionary in terms of functionality and capability. They are claiming that the chip will yield "desktop-like multimedia performance". This seems like a stretch if the chip were to include flash. Remember, the flash is not only used for storage, but also for XIP (eXecute In-Place) - there is no DRAM. I'm not sure that this kind of functionality would be possible from flash with its slow response time. This would also explain Intel's strained silicon move. I'm no expert, but I think that strained silicon facilitates OUM for one of the following reasons:
1) Increased drive current required for quick manipulation of chalcogenide memory element.
2) Adhesion - Intel's cost problems were apparently related to durability. The chalcogenide layer was not "sticking" to the standard silicon/CMOS materials so an intermediate layer ($) was required. With strained silicon, you've got germanium added to the mix. Germanium happens to be one of the elements in the chalcogenide (GeSbTe). Who knows...
In any event, I believe that the following could be true:
1) Intel's Prescott dissipates over 100 watts because it *includes* system memory (or even an on-chip "hard drive replacement"). Phase-change memory dissipates is quite dense and, thus, dissipates quite a bit of energy during read/write intensive operations. Perhaps this is also why Intel seemed to emphasize that this number was the "envelope" rather than a typical number. 100 watts *peak* might not be a lot if the average is significantly lower (remember, OUM is NVRAM so it does not require refresh power).
2) If there is one chip that will contain OUM, I think that would be Bulverde, as described above. At the meeting last week, Intel confirmed that they had OUM down to 2ns (200mhz) with durability in the 1E14 range - not *quite* DRAM/desktop range yet.
3) Intel is on the heels of introducing OUM en-masse. In terms of physical size, OUM has the potential to be 1/4th to 1/16th smaller than SRAM or DRAM (1 memory element vs. 4 or 6). This is remarkable but Intel have also patented 3-dimensional OUM. It is possible that a single "block" of OUM could replace an entire hard drive.
Questions? Comments? Complaints?
In particular, low programming energy is important when the EEPROMs are used for large-scale archival storage. Used in this manner, the EEPROMs would replace the mechanical hard drives (such as magnetic or optical hard drives) of present computer systems. One of the main reasons for this replacement of conventional mechanical hard drives with EEPROM "hard drives" would be to reduce the power consumption of the mechanical systems. In the case of lap-top computers, this is of particular interest because the mechanical hard disk drive is one of the largest power consumers therein. Therefore, it would be advantageous to reduce this power load, thereby substantially increasing the operating time of the computer per charge of the power cells. However, if the EEPROM replacement for hard drives has high programming energy requirements (and high power requirements), the power savings may be inconsequential or at best unsubstantial. Therefore, any EEPROM which is to be considered a universal memory requires low programming energy.
Of other interest is that Intel was supposed to announce Prescott on December 3rd at the MRS meeting on the heels of the Stanford Ovshinsky's nonbinary computing breakthrough announcement. FWIW, this technology is described in patent 6,141,241 and utilizes the same phase-change technology on which OUM is based.
Thus, the set pulse can be divided into a number of equal interval sub-interval pulses, each representing a data storage bit. For example, if it is desired to store in a single memory element a full eight bit byte NOTE - it looks like they meant 3-bit / 8-state , the sub-interval pulse magnitude and height can divided, in one embodiment, such that eight pulses are required to cause the device to switch to its low resistance state. Then, the eight storage levels would be from 0 to 7 pulses to store decimal values from "0" to "7". If 0 pulses are initially applied to the element to store a "0", for example, then 8 pulses are required to switch the element to its low resistance state and this can be read as a "0" by subtracting from the number 8 the number of pulses required to switch. Thus, the stored value can be determined in each case by subtracting from the number 8 the number of pulses required to switch the memory element to its low resistance state. For example, if a "7" is stored, the number of pulses required to switch the element to its low resistance state is 1, and the stored decimal value is thus "7". Various logic protocols can be selected for the storage and retrieval of information in the universal memory elements of the invention.
Will Intel be selling hard drive chips soon?