Everyone seems to be defining High Performance Computing as CISC/RISC chips with multi-core processors utilizing Instruction Level Parallelism and Thread-Level Parallelism with extremely fast multi-level Caching. HPC High Availability computing is a synergy of CISC/RISC chips combined with Application, Integrated Instruction, Facility, Graphic and Cryptography assisted processor technologies supplemented with Integrated Coupling facilities. These processors must share access to large amounts of fast Dynamic Random-Access Memory and be integrated into fast I/O bus architectures for a variety of High Performance connectivity with networking equipment, data storage, and other peripheral devices. All this hardware must work in concert with a variety of firmware, hyper-visors, and operating systems supporting telecommunications, storage management, databases, application run-time environments, application servers, web servers, online transaction servers, redundancy, security, applications, fail-over, backup, recovery, archival, and administration management. IBM has been doing HPC/HA for quite a while now. Hewlett-Packard, Oracle Sun Microsystems, Microsoft, Intel, EMC, and Cisco seem to be still chasing the dream.