This article is a bit deceptive. IBM is not trying to create a package with 1000 high-end, high-power CPUs in it. Clearly, this would require 1000 times the thermal capacity in the cooling system, not to mention 40kW power supply to drive it and a pair of 40kA copper rails to bring all that current (at 1V) into and out of the package. This is not happening. The issue IBM is looking at is silicon defects. If you make a single MIPS processor per die, then you can get 10,000 of them on a wafer. If that wafer suffers 100 random defects, then you still have 9900 good die for 99% yield. However, if you try to make 64-core processors that are fashionable today then you only have 156 units on your wafer and the same 100 defects leave you with only 56 prime dice, for 36% yield which is shit. IBM's big idea seems to be to manufacture the multi-core processors which can be assembled from a multiplicity of known good die. They aim to build 64-core CPUs, by stacking tiny single-core CPUs, not the 64000-core CPUs that I pictured when reading this article.