Comment Combined CPU and DRAM (Score 2) 211
Wow, we're on Slashdot......almost like being On The Cover of the Rolling Stone.
Answers to various questions and comments:
- We support the Linux toolchain; compilers, debuggers, etc., fortunate to have some of the original gcc team. Ported pieces of various kernels to TOMI Aurora to make certain we had not left anything out and to test the memory manager. Aurora was for use in a tablet type device.
- TOMI Borealis was optimized for Big Data and unstructured data apps like MapReduce that choke at the Memory Wall. Linux could probably be ported without too much difficulty. Most massively parallel installations will use something really light weight instead.
- Potential users said give them more integer cores instead of adding FPU. We gladly cede the FP world to Itanium.
- For raw FP horsepower within a reasonable power budget, its tough to beat Nvidia's GPU approach. That is probably why 3 of the top 10 supercomputers are GPU accelerated. http://www.top500.org/ GPU-type architectures will likely be the future of scientific computing. Venray is focused on Memory Wall limited areas such as Big Data.
- From the computer architecture perspective, the distinction between Big Data and Small Data is whether the datasets will primarily fit within the onboard caches. Video compression, graphics acceleration, encryption, and much of LINPAC (http://en.wikipedia.org/wiki/LINPACK) would be classed as Small Data since most of the computing can be done without leaving the caches (high locality). Legacy architectures choke on Big Data since the datasets overflow the caches and there is much much less data reuse.
- MapReduce is important because it is currently the most visible Big Data application thanks to Google. http://research.google.com/archive/mapreduce.html
- Venray believes Big Data applications are the future of computing. So does McKinsey Consulting. http://www.mckinsey.com/Insights/MGI/Research/Technology_and_Innovation/Big_data_The_next_frontier_for_innovation We leave it to others to accelerate MS Office and Call of Duty.
- The future of Big Data appears to be RAM resident, not disk, not even flash. (See Fred Ho's work at IBM.) https://www.ibm.com/developerworks/mydeveloperworks/blogs/fredho66/?lang=en_us
- re: Mitsubish 3DRAM and other similar ventures, iRAM, Exacute, Gilgamesh, etc....they embedded DRAM into logic. Contrast with TOMI that embeds CPU cores into DRAMs.....our benefits are performance and particularly cost: http://www.edn.com/photo/294/294788-microprocessor_vs_memory_transistors_graph.jpg
- We chose a modified RISC architecture rather than a special purpose one such as Gilgamesh in order to make programming simpler with well understood Linux tools such as gcc. Submit your gcc C, C++, or Fortran to http://www.venraytechnology.com./ Statistics are returned in standard dGen format.
- TSV (through silicon vias) and HMC (hybrid memory cube) are valid attempts to push back the Memory Wall. Discussed in Part 1 for EDN. http://www.edn.com/article/520059-The_future_of_computers_Part_1_Multicore_and_the_Memory_Wall.php Decision may be determined by cost.
- Would love to dispense with caches because they add transistors. 4K data and 4K instruction caches sped us up about 10x. Unlike legacy architectures, TOMI cache lines load in a single DRAM cycle.
- Yes love Raspberry Pi. http://www.raspberrypi.org/
- Quad-core adds about 20% to die size of 64M DRAM for TOMI Aurora. 8-core adds about 14% to 1G DRAM of TOMI Borealis.
- Yes love Chuck Moore. Moore/Fish patents paid for this: http://www.buildafricanschools.org/
- Yes to hash while you map. Search without indexing. See Fred Ho above.
- Yes to IBM Power7 using embedded DRAM. See explanation of differences from TOMI above and reasons they are important: http://www.edn.com/photo/294/294788-microprocessor_vs_memory_transistors_graph.jpg
- Love David May and his work on the Memory Wall and at XMOS. http://www.cs.bris.ac.uk/~dave/
- Love David Patterson, Patterson's Three Walls, and iRAM.......but does he love us back? http://www.cs.berkeley.edu/~pattrsn/
- First known description of CPU in DRAM in 1989: http://www.pat2pdf.org/pat2pdf/foo.pl?number=5,440,749
- Love Beowulf clusters. Talk to Sterling.
- That's 128k per core (1G/8).....not 128 words.
- If you care about the various architectural limits of Patterson's Walls see the EDN series:
http://www.edn.com/article/520059-The_future_of_computers_Part_1_Multicore_and_the_Memory_Wall.php
http://www.edn.com/article/520499-Future_of_computers_Part_2_The_Power_Wall.php
Part III is February
Good comments all.
Regards,
Russell
Answers to various questions and comments:
- We support the Linux toolchain; compilers, debuggers, etc., fortunate to have some of the original gcc team. Ported pieces of various kernels to TOMI Aurora to make certain we had not left anything out and to test the memory manager. Aurora was for use in a tablet type device.
- TOMI Borealis was optimized for Big Data and unstructured data apps like MapReduce that choke at the Memory Wall. Linux could probably be ported without too much difficulty. Most massively parallel installations will use something really light weight instead.
- Potential users said give them more integer cores instead of adding FPU. We gladly cede the FP world to Itanium.
- For raw FP horsepower within a reasonable power budget, its tough to beat Nvidia's GPU approach. That is probably why 3 of the top 10 supercomputers are GPU accelerated. http://www.top500.org/ GPU-type architectures will likely be the future of scientific computing. Venray is focused on Memory Wall limited areas such as Big Data.
- From the computer architecture perspective, the distinction between Big Data and Small Data is whether the datasets will primarily fit within the onboard caches. Video compression, graphics acceleration, encryption, and much of LINPAC (http://en.wikipedia.org/wiki/LINPACK) would be classed as Small Data since most of the computing can be done without leaving the caches (high locality). Legacy architectures choke on Big Data since the datasets overflow the caches and there is much much less data reuse.
- MapReduce is important because it is currently the most visible Big Data application thanks to Google. http://research.google.com/archive/mapreduce.html
- Venray believes Big Data applications are the future of computing. So does McKinsey Consulting. http://www.mckinsey.com/Insights/MGI/Research/Technology_and_Innovation/Big_data_The_next_frontier_for_innovation We leave it to others to accelerate MS Office and Call of Duty.
- The future of Big Data appears to be RAM resident, not disk, not even flash. (See Fred Ho's work at IBM.) https://www.ibm.com/developerworks/mydeveloperworks/blogs/fredho66/?lang=en_us
- re: Mitsubish 3DRAM and other similar ventures, iRAM, Exacute, Gilgamesh, etc....they embedded DRAM into logic. Contrast with TOMI that embeds CPU cores into DRAMs.....our benefits are performance and particularly cost: http://www.edn.com/photo/294/294788-microprocessor_vs_memory_transistors_graph.jpg
- We chose a modified RISC architecture rather than a special purpose one such as Gilgamesh in order to make programming simpler with well understood Linux tools such as gcc. Submit your gcc C, C++, or Fortran to http://www.venraytechnology.com./ Statistics are returned in standard dGen format.
- TSV (through silicon vias) and HMC (hybrid memory cube) are valid attempts to push back the Memory Wall. Discussed in Part 1 for EDN. http://www.edn.com/article/520059-The_future_of_computers_Part_1_Multicore_and_the_Memory_Wall.php Decision may be determined by cost.
- Would love to dispense with caches because they add transistors. 4K data and 4K instruction caches sped us up about 10x. Unlike legacy architectures, TOMI cache lines load in a single DRAM cycle.
- Yes love Raspberry Pi. http://www.raspberrypi.org/
- Quad-core adds about 20% to die size of 64M DRAM for TOMI Aurora. 8-core adds about 14% to 1G DRAM of TOMI Borealis.
- Yes love Chuck Moore. Moore/Fish patents paid for this: http://www.buildafricanschools.org/
- Yes to hash while you map. Search without indexing. See Fred Ho above.
- Yes to IBM Power7 using embedded DRAM. See explanation of differences from TOMI above and reasons they are important: http://www.edn.com/photo/294/294788-microprocessor_vs_memory_transistors_graph.jpg
- Love David May and his work on the Memory Wall and at XMOS. http://www.cs.bris.ac.uk/~dave/
- Love David Patterson, Patterson's Three Walls, and iRAM.......but does he love us back? http://www.cs.berkeley.edu/~pattrsn/
- First known description of CPU in DRAM in 1989: http://www.pat2pdf.org/pat2pdf/foo.pl?number=5,440,749
- Love Beowulf clusters. Talk to Sterling.
- That's 128k per core (1G/8).....not 128 words.
- If you care about the various architectural limits of Patterson's Walls see the EDN series:
http://www.edn.com/article/520059-The_future_of_computers_Part_1_Multicore_and_the_Memory_Wall.php
http://www.edn.com/article/520499-Future_of_computers_Part_2_The_Power_Wall.php
Part III is February
Good comments all.
Regards,
Russell
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It isn't easy being the parent of a six-year-old. However, it's a pretty small price to pay for having somebody around the house who understands computers.
