JHDL + clock gating = quick, large, low power (Score 1)

If you intend to use a high level hardware definition language, be prepared to have an implementation (netlist) that is not optimized for area (gate/register count) or power consumption. I beleive the only way to gain a smaller area is to be as explicit as possible in your JHDL code. However, if you can be smart about defining clock-gating (limiting the gates and registers that see clock transitions when not in use), you can solve the power consumption problem.