Comment Re:performance (Score 1) 191
How does pipelining help you retire more than 1 instruction per cycle? I'm sure that it is heavily pipelined, but AFAIK that only helps with reducing the CPI if it is larger than 1. I'm also sure that the chip is superscalar but 50GFLOPS sounds unrealistically high, the Fuzion 150 runs at 200Mhz, is MP SIMD with 1500+ processing elements and still does approx. 3GFLOPS.
You'd also need to have 200-300GB/s bandwidth to sustain that kind of speed (assuming a modest 16 bit-sized floats).
You'd also need to have 200-300GB/s bandwidth to sustain that kind of speed (assuming a modest 16 bit-sized floats).
