This really is not a task for programmers. It is a task for an engineer that has done both logic and software design.
I've been programming FPGA's since Xilinx came out with their first chips. At the time, it was all schematic capture. Place and route never completed on its own, it always required user editing to finish.
FPGA design techniques depend on your constraints. For some projects, it is much cheaper to buy a very large FPGA and not worry about space optimization. If you are building thousands of the same device, then space optimization is critical. For other projects, logic timing is everything.
Every chip has it's own constraints as well, especially if speed is an issue. When speed is an issue, you have to really understand how your VHDL will be implemented, because it will make all the difference between sucess & failure.
Learning how to use constraint files is important. Learning how to test using simulations is critical. Time spent writing and runing simulations may exceed design time for an order of magnitude.