The facts is, data density on solid state has already surpassed data density on magnetic/spinning media. We already have 4TB SSDs at SanDisk, and 8TB and 16TB drives are on the horizon. I highly doubt you'll see HDD do 16TB in a 2.5" package anytime soon. Also, when you factor in power requirements, the economics start to look very favorable to SSD, not 10K or 15K RPM drives which are used in latency-sensitive applications. And, in another unexpected and non-intuitive twist, SSDs have a much higher MTBF then HDDs, around 2.5M hours vs. 1.1M hours. Wear-out has become a non-issue, even in the harshest environments. There are SSDs that are rated for anything from less than 1 Drive Write Per Day (DWPD) on up to 45 DWPD during the length of warranty (usually between 3 and 5 years). Bottom line, SSDs are a far better economical choice in many cases. Of course, this only matters where economics count. Enthusiasts are already seeing the benefit in lower prices and higher densities, but the OP is not about them. Economics is not about "can the consumer afford it" as much as it is about "does this enable me to lower my TCO in the data center". We are there already.

No, but maybe I should start writing them.

I think a lot of commenters on this are missing the point that 16 lanes of PCI-e 3.0 directly on-die is going to be a massive boost to Native PCI-e NAND Flash implementations (Fusion-io, for example). One of the biggest hurdles to getting more productivity out of faster CPUs and the proliferation of sockets/cores is feeding data to those CPUs. The disparity here is staggering... CPUs have improved by over a million times where storage interfaces and devices have only improved perhaps 100x (being generous) in the same timeframe. This change puts many terabytes of native PCIe NAND flash memory in very close proximity to the CPU complex and will enable vastly more efficient applications.

This type of reader has very good specifications regarding false-positives and false-negatives.

The basis of the technology is that it constructs an image of the fingerprint based on variations in the electrical resistance over the surface of the living finger - please note the word "living." The exterior surface of your skin, including the finger, is dead. Strip off the upper few layers of dead skin cells and you find the first layer of living skin cells. These skin cells have specific qualities of electrical resistance. They also composed into specific shapes over the surface of the skin. The combination of specific electrical qualities in the cells and specifically how the cells are arranged results in measurable and unique variations of electrical resistance over the surface of the finger. That is what a capacitive fingerprint sensor does - it reads variations in the electrical resistance of the living surface of the finger and constructs a map of the finger that shows those variations.

I don't think the variations caused by stress or illness would be enough to skew the reader to get a false-negative reading (user fails to login with correct finger). If you think about the fact that the user is dragging the finger across the reader at infinitely variable speeds (even though only a relatively small range of speeds will work), you'll realize that the mapping technology is pretty advanced, so the very slight variations introduced by stress or illness would not interfere.