I still have one of those Intel keychains. I'll have to go back and take a closer look at it.
Ah, MOSIS. That certainly brings back the memories. Back in the early 1990s I worked as the IT guy for the Electrical Engineering Department of a certain state university (to be left unnamed for reasons you'll understand here). We had just received our first student-designed chip fabricated by MOSIS, which came as several packaged ICs with what I recall to be a nice 8x10 photomicrograph of the die.
Right in the middle of the die, in capital letters 50 microns tall on the die but larger and oh-so-legible on the 8x10, was the phrase:
XX SUX
where "XX" is the common abbreviation for another (larger) state school that was our rival in every way: sports, money, facilities, sports. I was the unfortunate soul who delivered the photo to the faculty member in charge of the grad student designers and had to explain "XX SUX" to the foreign-born professor. He was unfamiliar with the phrase and for some reason I chose to use the oral sex origin of the expression rather than just glossing it over and saying it meant the other school was really bad. It was... an uncomfortable conversation.
I'm pretty sure it was a bit of a political problem for the professor. Designing and fabrication of a chip was a pretty big deal, as it was a first for our state and was going to be given the dog-and-pony show treatment to seek more funding from our legislators so we could improve our program and fabricate more chips. Unfortunately, our state government was/is heavily favorable to "the other guys" and the insult encoded in silicon wouldn't have been very well received. I still remember the bit of carefully-placed Post-It note covering the inscription at the center of the photo when it was displayed in the glass case outside of the lab and in the copies given out for publicity and and in funding proposals.
A second memory: I dealt with a team of brilliant - but very hard to restrain - grad students who were always trying to push the boundaries of what was allowable. They had worked out the reflectivity of the various layers of a chip: metal, oxide, polysilicon, etc and had written software that took a 128x128 image and used dithering of the reflectivities to render the image into something that could be inserted into a chip design. The image would be viewable in reasonable grayscale when the die was viewed from a certain angle. Most importantly, the rendered pattern would pass all of the verification rules that helped prevent the submission of invalid semiconductor designs. (Btw, please forgive me if I have some of the terminology incorrect here; I'm not an EE and in any case it's been 30+ years, but you get the idea.)
The one big problem was that MOSIS rules at the time disallowed any logos, etc more than 50 microns tall. The grad students wanted to put one of their faces on a corner of the chip they were designing but the image would have been larger than allowed. I went around and around with the students about this and ended up contacting MOSIS for an exception, giving their justifications: The pins on the chip were fully-utilized so there were no unused functions they could have added for external testing, the image would be using otherwise empty space on the die, we couldn't have eliminated the empty space to use a smaller die, etc, etc, etc.
Unfortunately, the final answer from MOSIS on this was "no", and I don't recall what they eventually did with the empty space.
Thanks for the trip down memory lane!
