Religion and design aesthetics aside, the commercial advantage of RISC was entirely a consequence of the fab process capabilities of the time RISC was introduced. At any given process, you can fit only so many gates on a die before yield goes to hell completely and only the government can afford to buy the chips. RISC uses fewer gates than CISC because it's a much simpler decode. So at some process you can fit a reasonable RISC processor on a cheap enough chip where you couldn't fit the same capability in CISC on the same chip. Alternatively and equivalently, you could fit a dinky CISC or a more capable RISC on the chip.
That edge process happened about 1980, and lasted for two fab generations ending around 1985. Then the fabs got good enough that you could fit either CISC or RISC, your choice, and the commercial advantage of RISC ISAs went away. The formerly dinky CISC got jazzed up by true designer heroics, and today you choose an architecture based on other reasons.
There remain a few markets where cheap (power and area) decode still matters enough to influence dollar decisions. Mobile is one, and CISC as she is spoke in x86 is at a disadvantage. However, most posters seem to assume that CISC necessarily has expensive decode, and that CISC == x86. Both assumptions are false.
