FPGAs can't be tested for races (Score 2)

You can test the logic (high level) design of circuits on an FPGA, but CBL (Clocked Boolean Logic) design is sensitive to races - unlike alternative logics that are delay-insensitive (and asynchronous!) such as Theseus' Null Convention Logic (NCL).

Having said that, rapid prototyping using FPGAs, such as Xilinx's contribution to artificial intelligence research can be neat.