I think you might misremember a little bit.
The 68k CPU was a CISC design using microcode, which meant that one instruction took multiple clock-cycles to execute (minimum of 4 cycles). Basically, it spent one clock cycle accessing memory and one clock cycle for internal processing.
The designer's exploited this by having DMA during the memory on odd cycles when the bus was free. Audio DMA had four statically allocated DMA slots per raster line, which did not interfere with the CPU, meaning that even if you turned off all audio DMA, the CPU wouldn't run any faster, because it didn't use those slots anyway (of course, the copper or blitter could make use of them if needed though!)
Where it got interesting was with bitplane DMA, because there wasn't enough bandwidth to sustain both display and CPU at full speed if more than four bitplanes were enabled (lores), and then cycle stealing started. Turn on high res and four bitplanes and the bitplane DMA consumed all memory slots except during v-sync and h-sync!!
On top of that, the copper and the blitter also competed for the same cycles as the CPU. The "CPU danger bit" that you remember was actually the "blitter nasty" flag, which gave the blitter ultimate priority over the 68k.
The copper always had priority over both the blitter and the 68000 and would steal as many cycles as it needed, potentially every one.