Start with verilog and graduate to VHDL (Score 1)

First the quick answer - for what you need to do/achieve, Verilog sounds like the right choice. Focussing on digital design basics and synthesis is, IMO, far more important and crucial for beginners than worrying about language constructs. Although I wouldn't take that arguement too far and advocate that schematic entry is an acceptable choice instead of RTL. VHDL or Verolog will not teach you digital design. Just like C/C++ will not teach you computer architecture. VHDL vs Verilog choice becomes more important when the project's size (people) and complexity grows. For large and complex projects VHDL offers far more powerful constructs like generic programming (unconstrained ports) and abstraction (multiple entity-architecture, configuration etc) and the verbosity/cumbersomeness of the language is easily offset by the benefits. I have been an avid VHDL user for over 10 years. For sufficiently complex projects I have been able to convince and convert verilog users to adopt VHDL except for my current project where some people still use schematic entry - SIGH.