| Subject | Datestamp | Replies | Score | |||
|---|---|---|---|---|---|---|
| Re:VHDL + FPGA | ||||||
| attached to gEDA (GPL'ed Electronic Design) In EE Times | ||||||
The decision doesn't have to be logical; it was unanimous.
| Subject | Datestamp | Replies | Score | |||
|---|---|---|---|---|---|---|
| Re:VHDL + FPGA | ||||||
| attached to gEDA (GPL'ed Electronic Design) In EE Times | ||||||
The decision doesn't have to be logical; it was unanimous.