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Comment Re: Where are those chips baked? (Score 1) 47

You are correct that the standard cell library is going to be proprietary to the fab and therefore out of our control. It will also be produced using proprietary synthesis and place and route tools, which is currently the only feasible way. That said, some people like efabless are using Yosys for synthesis on older process nodes (180nm+).

Comment Re:Where are those chips baked? (Score 1) 47

Just to be clear, lowRISC is a separate project to the RISC-V instruction set architecture, though we are lucky enough to have Krste Asanovic on our technical advisory board and are working with the Berkeley team. The results for the 'Rocket' core from Berkeley are using TSMC 40nm, but that isn't necessarily what we will produce lowRISC on.

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