First ever slashdot contribution (Score 2, Insightful)

Finally a topic I care enough to go register in order to put in my opinion... Let's see how bad I get slammed :) I work in FPGA's and have done a couple of relatively small projects in them. I have exclusively used VHDL. But after I taught myself VHDL, reading Verilog is pretty easy. It is a Coke / Pepsi thing because you are asking for a "better" decision. Most jobs can be done by either language. VHDL is preferred in some circles, especially military / DOD / Aerospace (where I work). Verilog has a shallower learning curve for those used to sequential programming languages like C. VHDL is more powerful if you can think in terms of the underlying digital hardware (propagation delays, clock hold times, clock domains, etc). And not to be too pedantic, but VHDL is NOT a programming language. A programming language is something that ultimately is translated into a series of instructions for a processor. VHDL is a hardware description language. You are actually describing a piece of hardware that will be implemented as a set of gates on a piece of silicon. VHDL code will never result in instructions and will never be "ran". It will be implemented in hardware and will respond to inputs and produce outputs per your design. My answer, it depends on your goal. If you want to produce a more rounded CS major capable of understanding this aspect of technology, focus on teaching Verilog with some VHDL examples to highlight the differences. If you want someone that could go produce useful work after graduation, focus on VHDL. I know I will probably be unpopular because Verilog is more prevalent among the "traditional" programmers because it is an easier leap from C.