Speculative emulation of CISC machine instructions (Score 1)

This device supports speculative emulation of CISC machine instructions. If TransMeta is really implementing this device, it appears to me that they're developing a very high performance RISC machine that will be able to emulate the X86 architecture at a speed significantly faster than the current generation of Pentiums.

Speculative execution makes it possible to optimize conditional branches so that they take no more time to execute than a non-branching instruction stream. In order to do this, the processor "sees" the branch coming in its lookahead buffer. It then begins fetching instructions located at both possible branch targets and executes them "speculatively" before the branch is reached. This is speculative execution because the processor doesn't know which branch path will be taken.

On a RISC machine, very few instructions reference memory, so it is easy to execute long instruction streams speculatively without the possibility of incurring a page fault. This is not the case with CISC architectures like the x86 family. Here, you can easily have three-address instructions that load two operands out of memory, add them together, and store the result at a third address. All three of these memory references can generate a page fault, which themselves cause a branch to the OS's interrupt handler.

The new device simply makes it possible for the emulator to speculative execute these instructions as long as they don't generate a page fault. When the original branch is ready to be executed, the processor checks the speculatively emulated instructions in the chosen path. If they completed without error, the device is instructed to write out the contents of its local store for any memory locations that were changed. The processor then continues to execute at the instruction after the speculative execution, without ever experiencing a pipeline stall.

If the chosen branch path that was speculatively emulated would have resulted in a page fault, the device is instructed to write out any stores that did not cause a fault, and then take the page fault. In this case, the pipeline will stall, but this stall could not have been avoided, because the page fault was inevitable.

Dave Ditzel (the founder of TransMeta) was the principal architect for the SPARC-V9 64-bit RISC machine. The SPARC Architecture Manual-V9 contains extensive information about branch prediction and speculative execution. You can get it on Amazon.