Your description isn't terribly accurate either. Back in the days of planar semiconductors, the process node (eg. 45nm, 32nm, 22nm) referred to the minimum feature size, which was also at least approximately the minimum gate length. There are other features, particularly some metal line widths in the Back End Of Line (BEOL) that were also close to the nominal node size. The problem in modern technology is that as you scale down the gate length, short-channel effects, particularly Drain Induced Barrier Lowering (DIBL) begins to dominate. This effect degrades transistor performance, such that it is no longer practical to scale gate lengths much below ~20nm. We could easily print 7nm gates, but the resulting devices would be power hungry, hot and slow, not exactly the combination anybody wants!
Now having said that, some gate scaling is still possible, but whereas in the past, gates were routinely scaled by ~30% between each node, today gate scaling is on the order of a few percent and even that requires a lot of work to optimize the device junctions, so as to constrain DIBL. Nevertheless, there are still gains to be had by scaling other aspects of the device. Moving to Finfets, where the gate wraps around a "fin" of silicon provides two advantages. First, the fin itself has a vertical dimension, which corresponds roughly to the width of conventional planar device. This means that if we want more current per unit area, instead of widening the transistor, we can make the fin taller (within limits). So, we are kind of scrunching the transistors into a smaller space. The other and perhaps more important advantage is that because the gate wraps around a very thin fin of silicon, it has better control of the silicon channel, reducing DIBL and other short channel effects. Thus, thinning down the fin provides not only a density benefit, but also a performance benefit.
In today's technology nodes, the smallest dimensions no longer correspond to the gate length, but they do correspond roughly to the fin size. As far as I'm aware, all of today's 7nm processes consist of Fins in the 6-9nm range. I believe there are also some metal lines that are of similar size, which helps in providing more flexibility in routing the connections between various circuits.
Finally, regarding comparing technologies between fabs, the comparison is somewhat complicated by some specific design choices about the basic SRAM and Logic cells and how they are allowed to be connected. In particular, Intel's 10nm process, uses a very aggressive BEOL. This allows them to make small cells of comparable density to the 7nm process of Samsung and TSMC. By contrast, Samsung and TSMC have a relaxed BEOL, so they sacrifice some density, but retain a lead in the raw transistor performance. The end result is that intel's 10nm process and 7nm processes of their competitors are all very comparable.