Well, they built the aqueduct...

Verilog gives you enough rope to easily hang yourself. VHDL gives you so little rope you'll want to hang yourself. As a vehicle for teaching H/W design though, I think VHDL would be better. It's much more explicit and rules oriented, and looks like you're describing H/W. Once you've learned VHDL, picking up Verilog is fairly trivial. I would think going in the other direction would be a bit harder. Language Bias Disclaimer: I've been using VHDL for 10 years, and Verilog for 2...

Umm, EVERYONE normal in Norway...hmmm no not so much. Anyone familiar with the Black Metal scene http://en.wikipedia.org/wiki/Early_Norwegian_black_metal_scene and the suicide/murder shenanigans between Mayhem and Burzum might not call that behavior normal. You know, rearranging your dead friends body for pictures, making necklaces out of his skull, all sorta not normal in my world...

All my life, in my surroundings, if someone asked you the date something was going to happen, you'd say "August 22nd"

Wow, what a boring place. What did you guys do for the other 364 days?