Comment Re: Wrong math, was Re:compilers (Score 1) 589
Lets get this physics right:
First, it is the speed of the electromagnetic wave that counts, and (indeed) in free space it does travel at C.
Second, EM waves in silicon have to deal with the permitivity of the oxide (insulating) layers, slowing the speed of the wave to no better than 0.5 C (Pe[SiOx] = 3.9).
Third, The copper signal traces have resistance which slows the edge speed of a signal. Even though the first vestiments of the signal edge arrives with time delay close to 0.5 C * l, the last vestiments of the edge do not arive until ~R*C later.
Forth, at the edge speeds of processors just entering design (for customers in 2005+) the skin effect becomes significant (making the effective resistance of signal traces larger).
Fifth, there must be sufficient signal to overcome any residual noise in the proximity of both the sender of the signal, and the receiver of the signal. And much of the time, this signal must transition from one defined value (VIL) to another (VIH) within a given time (10% of a cycle).
So even if the speed of the EM wave is ~0.5C, the speed of a rail-to-rail sent signal and VIL to VIH received signal is R*C limited. With a typical 0.1um process, the maximum distance you can send a signal with an edge faster than 0.2 cycles is about 5 mm (10 GHz==100 ps cycle time design point) with optimal repeaters and wire spacing. With a typical 0.18um process and a 2 GHz cycle time, one can achiev on the order of 15 mm distance (also with optimal repeaters). Both of these signaling speeds are on the order of 1% to 3% of the speed of light. Its a shame, but it is also reality.
This distance can be increased with:
a) slower processor design points (yeah right)
b) low permitivity dielectrics
c) smaller cladding in the copper metalurgy
d) superconducting wires (yeah right)
e) non-wire-based signaling (e.g. radio waves)
f) optical interconnects on-die
First, it is the speed of the electromagnetic wave that counts, and (indeed) in free space it does travel at C.
Second, EM waves in silicon have to deal with the permitivity of the oxide (insulating) layers, slowing the speed of the wave to no better than 0.5 C (Pe[SiOx] = 3.9).
Third, The copper signal traces have resistance which slows the edge speed of a signal. Even though the first vestiments of the signal edge arrives with time delay close to 0.5 C * l, the last vestiments of the edge do not arive until ~R*C later.
Forth, at the edge speeds of processors just entering design (for customers in 2005+) the skin effect becomes significant (making the effective resistance of signal traces larger).
Fifth, there must be sufficient signal to overcome any residual noise in the proximity of both the sender of the signal, and the receiver of the signal. And much of the time, this signal must transition from one defined value (VIL) to another (VIH) within a given time (10% of a cycle).
So even if the speed of the EM wave is ~0.5C, the speed of a rail-to-rail sent signal and VIL to VIH received signal is R*C limited. With a typical 0.1um process, the maximum distance you can send a signal with an edge faster than 0.2 cycles is about 5 mm (10 GHz==100 ps cycle time design point) with optimal repeaters and wire spacing. With a typical 0.18um process and a 2 GHz cycle time, one can achiev on the order of 15 mm distance (also with optimal repeaters). Both of these signaling speeds are on the order of 1% to 3% of the speed of light. Its a shame, but it is also reality.
This distance can be increased with:
a) slower processor design points (yeah right)
b) low permitivity dielectrics
c) smaller cladding in the copper metalurgy
d) superconducting wires (yeah right)
e) non-wire-based signaling (e.g. radio waves)
f) optical interconnects on-die
