The processors being discussed are not the lean ARM processors you would find in a phone or tablet. These chips are designed for servers. The Cavium chips, for example, are designed to handle an insane amount of memory bandwidth with a lot of cores, far more cores than Intel offers.
The Cavium cores are lean in the sense that they do not support the older 32-bit ARM instructions or the baggage they bring, i.e. they only support AArch64, not ARMv7. The switch from 32-bit to 64-bit ARM is more radical than the change between X86 and X86-64. A lot of what made ARM 'ARM' is gone. AArch64 is basically a new modern RISC instruction set incorporating everything that has been learned in the last few decades while throwing out much of the cruft that holds back performance. While some things may have been a good idea at the time they later proved to be a hinderance. While many of the instructions may look similar (and even have the same mnemonic), the encoding is completely different. The register set is also completely different. Instead of 16 registers (where the PC was one of the registers) there are now 31 general purpose registers (R31 is always 0 (like MIPS R0) except when it is the stack pointer). See Wikipedia.
The problems with the 32-bit ARM instruction set that prevented out of order execution and issuing multiple instructions in parallel are pretty much gone. Conditional ALU instructions are gone (except branch instructions) and the PC is no longer a general purpose register. There are also now 31 general purpose registers with register r31 having special meaning. It is generally always zero, much like r0 on MIPS, though there are also special instructions so it can be used as a stack pointer. It also doubles the number of 128-bit NEON registers from 16 to 32.
There are other Cavium CPU chips that are targeted at high-speed network devices with a lot of built-in engines for things like networking (10 and 40Gbps networking is built-in), encryption, RAID, compression and a number of other interesting engines useful for big data.
The X86 platform has a lot of warts that make some things very expensive for backwards compatibility. I'm amazed that they get as much performance out of it as they do given how horrible the instruction set is.
These chips can handle Windows just fine.
Full disclosure: I work for Cavium though I'm primarily involved with their MIPS processors.