Re:My initial response is "wow!!" (Score 2)

Well, as you stated yourself, reducing the gate area you reduce the gate capacitance. Thus you can still achieve the same charging time, albeit with a smaller voltage.

And as for power consumption, yes, if you do full scaling where every part of the device is scaled down by some factor X then you get a reduction in power consumption. However, with the wonders of backwards compatibility and meeting external specs and such, oftentimes the devices are not scaled down using full scaling. In this case the voltage is kept the same and the device size reduced, which actually leads to higher power consumption.

Of course it reaches a point where the power consumption is just obscene, at which point they reduce the operating voltage. And this really isn't a problem if you're going to put out a new chipset for the processor, just dictate what the voltages have to be. However, if you're trying to build in compatibility for an older chipset that doesn't support the lower voltages your chip requires, your SOL.