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Comment Kiribati has gotten larger (Score 1) 61

From âoe Historical area and shoreline change of reef islands around Tarawa Atoll, Kiribatiâ

https://link.springer.com/arti...

âoe Reef islands have substantially increased in size, gaining about 450 ha, driven largely by reclamations on urban South Tarawa, accounting for 360 ha (~80 % of the net change). Widespread erosion and high average accretion rates appear to be related to disjointed reclamations. In rural North Tarawa, most reef islands show stability, with localised changes in areas such as embayments, sand spits and beaches adjacent to, or facing, inter-island channels. Shoreline changes in North Tarawa are largely influenced by natural factors, whereas those in South Tarawa are predominantly affected by human factors and seasonal variability associated with El Niñoâ"Southern Oscillation (ENSO). However, serious concerns are raised for the future of South Tarawa reef islands, as evidence shows that widespread erosion along the ocean and lagoon shorelines is primarily due to human activitiesâ

The locals should also stop stealing aggregate from beaches (to make concrete), stop over-pumping fresh groundwater, and stop contaminating ground water with septic systems.

Comment Re:Process != actual size (Score 1) 35

The node name many years ago used to match the polysilicon gate length. Each subsequent node was 0.7 times the prior one. I.e., the shrink factor is 0.7. Note that 0.7 * 0.7 = 0.49, or roughly 0.5 — so transistors on the new node take up 1/2 the space of the prior. Put another way, you can put twice as many transistors in the same chip area. This is the key — the transistor budget doubles each generation. Other benefits, such as increased transistor drive strength. However, the area available to route signals is cut in half, so you have to add metal layers to maintain routing ability.

As the technology advanced, lithography wasn’t able to maintain the 0.7 shrink. However, other methods were used to double the transistor budget. So the node name doesn’t match the polysilicon gate length, but the transistor density was still doubled — maintaining the overall 0.7 shrink factor. Advanced transistor engineering brought other improvements. It used to be that pmos transistors had 1/2 the transconductance of nmos transistors. So pmos gate would have to be 2X wider than the nmos gate to have a balanced cmos driver. Now, through gate strain and other methods, the pmos transconductance is matched to nmos.

Maximum chip size is limited by the exposure field size of the litho tools — which is roughly the size of your thumbnail. Think of new nodes just communicating that the next node can put twice as many transistors in that thumbnail-sized area.

Why has this transistor doubling been achieved every node for decades now? Executive bonuses. In TD, executive bonuses are tied to achieving that doubling.

Comment Re: Need more nuclear fission power (Score 1) 224

It's a failed technology.

Sure, it can generate steam to power turbines. The waste "problem" is overblown and easily solved.

No, they are a failure because they cost too much and always are delivered years behind schedule. Georgia Electric bought two nuclear reactors for $35 billion that came in 7 years late.

Very few utility companies have the balance sheet to finance such capital expenditures and assume the risk of 2X+ cost overruns.

The plants work, but they cost too much and aren't delivered on time. FAIL.

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